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Q&A

ADE7933 layout guidelines - Lazy Y capacitor?

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ADE7933 contains an isolated DC-DC converter (Page 82). The control uses ~1MHz PWM signal with unknown rise time, but assuming something like 10ns, most of the energy would be contained in the 35MHz band based on:

$f_{\text{max}} \approx \frac{0.35}{t_r} \approx \frac{0.35}{10 \times 10^{-9}} = 35\,\text{MHz}$

Knowing that the winding capacitance can cause common mode noise issues, a 'Y' capacitor is often added between the windings to provide return path for the common mode current back to primary. However, this datasheet suggests to use PCB itself to create the same effect (Page 92):

Image_alt_text

This seems like a 'lazy' Y capacitor that is heavily dependent on the layout around the board to form this interplanar capacitance between primary and secondary. The value is not possible to tune. It also seems that this has to be extensively documented, since if the stackup was to change, this could introduce a safety risk. What I am wondering is why go through all this, if a discrete component can achieve the same performance? Are there any advantages of this approach besides saving cents on a discrete Y capacitor?

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This capacitance from the overlapping planes connects across the isolation barrier. Thus it's probabl... (1 comment)

1 answer

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I have a hunch that the AC which flows through the isolation transformer has quite a bit higher frequency than 1 MHz. The first piece of evidence is this sentence in the datasheet.

Each time a PWM pulse is generated, the ac source transmits very high frequency [VHF, emphasis mine, N.A.] signals across the isolation barrier to allow efficient power transfer through the small chip scale transformers.
[p. 82 in the ADE7933 datasheet]

The second piece of evidence is that Analog Devices has other isolated DC-DC converters with chip scale transformers (ADuM5242 among others). They are covered by an EMC application note AN-0971, which mentions up to 300 MHz in the opening sentence. Most of the app note is about the cap between the PCB ground planes.

What I am wondering is why go through all this, if a discrete component can achieve the same performance? Are there any advantages of this approach besides saving cents on a discrete Y capacitor?

The PCB plane capacitance has the important advantage that it comes with the least series parasitic inductance, compared to SMT capacitors. The only way to make a low inductance connection is with a broad flat object, and that's what power planes are. PCB vias add series inductance. Many parallel vias reduce the inductance.

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Appnote makes it clear, thanks! (1 comment)

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