Netlist extraction will create top-level circuits for circuits without connections to their parent

[klayoutmatthias]

This is for example true for filler cells without pins.

In some application this makes sense, in others not. Specifically when tracing nets, "flatten" will leave these top circuits so effectively the netlist isn't flat, but consisting of multiple top cells. For this application, non-connected cells should appear as subcircuits without connections inside their parent.

[lukasc-ubc]

Hi Matthias Do you have any plans to include optical netlist extraction? Similar to what we did in SiEPIC-tools? Lukas Chrostowski Professor, ECE University of British Columbia 604-822-8507 http://www.mina.ubc.ca/lukasc http://siepic.ubc.ca

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On Nov 19, 2019, at 3:27 PM, Matthias Köfferlein ***@***.***> wrote:  This is for example true for filler cells without pins. In some application this makes sense, in others not. Specifically when tracing nets, "flatten" will leave these top circuits so effectively the netlist isn't flat, but consisting of multiple top cells. For this application, non-connected cells should appear as subcircuits without connections inside their parent. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or unsubscribe.