[TRTLLM-10296][fix] Fix the potential misaligned access due to vectorized ld/st instructions in NVLinkOneSided A2A.#10539
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📝 WalkthroughWalkthroughThe changes refactor memory management in MOE all-to-all operations to enforce cache-line alignment requirements. A global alignment constant is introduced in C++, and workspace size calculations across multiple files are reworked to accumulate sizes incrementally with explicit alignment padding rather than computing separate components. Alignment validation checks are added for data pointers. Changes
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Actionable comments posted: 4
🤖 Fix all issues with AI agents
In @cpp/tensorrt_llm/thop/moeAlltoAllOp.cpp:
- Around line 254-259: The TORCH_CHECK message mislabels
offsets[PAYLOAD_DATA_OFFSET_INDEX] as "auxiliary data + payloads" when it is
actually the starting offset (auxiliary data size); update the check in the
block around requiredSize/currentOffset/sizePerRank/TORCH_CHECK to either remove
the erroneous breakdown or show an accurate breakdown: compute auxSize =
offsets[PAYLOAD_DATA_OFFSET_INDEX] and payloadsSize = currentOffset - auxSize
and include those values in the error text so the message reports "need at least
X bytes (Y aux + Z payloads), but got sizePerRank" or simply drop the
parenthetical breakdown.
- Line 426: Fix the comment "Typially, newly allocated torch tensors are at
least 16-byte aligned." by correcting the typo to "Typically" and removing the
incorrect guarantee about 16-byte alignment; replace it with a brief note that
PyTorch does not guarantee 16-byte alignment for allocations (CPU uses runtime
allocator aligned to alignof(void*), CUDA alignment varies) and state that
strict alignment must be verified explicitly or enforced via a custom allocator
or explicit checks where alignment-sensitive code (e.g., any buffer-alignment
logic near moeAlltoAllOp or related tensor handling) depends on it.
In @tensorrt_llm/_torch/distributed/moe_alltoall.py:
- Around line 57-82: The code calls pad_up(workspace_size, 128) several times
but ignores its return value; update each call to assign the aligned result back
to workspace_size (e.g., replace pad_up(workspace_size, 128) with workspace_size
= pad_up(workspace_size, 128)) after computing auxiliary size from
MoeAlltoAll.get_aux_data_size and after each incremental addition (unquantized
token hidden states, token_selected_experts, token_final_scales, extra payload
bytes per token, and the combine workspace) so the alignment is actually applied
before returning workspace_size.
In @tensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.py:
- Around line 84-109: The calls to pad_up(...) are currently ignored so
alignment is not applied; update each invocation to capture its return value by
assigning back to workspace_size (e.g., workspace_size = pad_up(workspace_size,
128)) for all occurrences in the workspace computation block that uses
workspace_size (within the NVLinkOneSided workspace calculation routine),
ensuring each alignment call updates workspace_size after adding the unquantized
token states, token_selected_experts, token_final_scales, extra payload bytes,
and the combine workspace.
🧹 Nitpick comments (3)
tensorrt_llm/_torch/distributed/moe_alltoall.py (1)
62-62: Fix typo in comment.The comment has a typo: "size,i" should be "size, i" (missing space after comma).
📝 Proposed fix
-# but due to the variety of quantization recipes, we cannot know the exact size,i +# but due to the variety of quantization recipes, we cannot know the exact size, icpp/tensorrt_llm/thop/moeAlltoAllOp.cpp (2)
36-36: Rename constant to follow naming convention.Per coding guidelines, constants should use uppercase snakecase with prefix 'k' (e.g.,
kCachelineAlignment).♻️ Proposed fix
-static constexpr size_t CACHELINE_ALIGNMENT = 128; +static constexpr size_t kCachelineAlignment = 128;Note: This change would require updating all references throughout the file (lines 72, 77, 82, 88, 94, 243, 264, 337).
As per coding guidelines, constant naming should use kPascalCase pattern.
337-337: Minor redundancy:currentOffsetis already aligned.At line 243,
currentOffsetis aligned toCACHELINE_ALIGNMENTafter each payload. When the loop completes,currentOffsetis already aligned, so thealignOffsetcall here is redundant.However, this is defensive programming that protects against future code changes and has no performance impact.
♻️ Optional simplification
- int64_t combinePayloadOffset = static_cast<int64_t>(alignOffset(currentOffset, CACHELINE_ALIGNMENT)); + // currentOffset is already aligned after the loop + int64_t combinePayloadOffset = static_cast<int64_t>(currentOffset);
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cpp/tensorrt_llm/thop/moeAlltoAllOp.cpptensorrt_llm/_torch/distributed/moe_alltoall.pytensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.py
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🧠 Learnings (10)
📓 Common learnings
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
Repo: NVIDIA/TensorRT-LLM PR: 6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.
Applied to files:
tensorrt_llm/_torch/distributed/moe_alltoall.py
📚 Learning: 2025-08-19T03:35:20.866Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.
Applied to files:
tensorrt_llm/_torch/distributed/moe_alltoall.pytensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.pycpp/tensorrt_llm/thop/moeAlltoAllOp.cpp
📚 Learning: 2025-08-09T20:57:04.084Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.
Applied to files:
tensorrt_llm/_torch/distributed/moe_alltoall.pytensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.pycpp/tensorrt_llm/thop/moeAlltoAllOp.cpp
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.py
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.py
📚 Learning: 2025-08-14T23:23:27.449Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Applied to files:
cpp/tensorrt_llm/thop/moeAlltoAllOp.cpp
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device allreduce implementation (cpp/tensorrt_llm/thop/allreduceOp.cpp), the goto pattern in runNCCLAllReduceDeviceFusion is intentionally used for future extensibility, allowing multiple switch cases to fallback to the default handler. While not aesthetically ideal, this pattern supports adding more fusion cases later that can reuse the same fallback logic.
Applied to files:
cpp/tensorrt_llm/thop/moeAlltoAllOp.cpp
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Applied to files:
cpp/tensorrt_llm/thop/moeAlltoAllOp.cpp
📚 Learning: 2025-09-23T14:58:05.372Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.
Applied to files:
cpp/tensorrt_llm/thop/moeAlltoAllOp.cpp
🧬 Code graph analysis (2)
tensorrt_llm/_torch/distributed/moe_alltoall.py (1)
tensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.py (1)
get_aux_data_size(71-72)
tensorrt_llm/_torch/modules/fused_moe/communication/nvlink_one_sided.py (2)
tensorrt_llm/_torch/distributed/moe_alltoall.py (1)
get_aux_data_size(44-46)tensorrt_llm/llmapi/llm_args.py (1)
ep_size(388-392)
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🔇 Additional comments (5)
cpp/tensorrt_llm/thop/moeAlltoAllOp.cpp (5)
207-218: LGTM! Well-documented alignment strategy.The comments clearly explain the three-part alignment guarantee:
- Base workspace pointer is validated (checked at line 264)
- Starting offset is aligned by
calculateOffsets- Per-payload offsets maintain alignment during updates
This ensures recv buffers meet the 128-byte alignment requirement for vectorized load/store operations.
226-244: LGTM! Proper alignment enforcement for payloads.The 16-byte alignment check for input payloads is appropriate since these tensors are allocated externally. The recv buffer offset calculation correctly maintains cache-line alignment by:
- Recording the current aligned offset
- Adding the payload size
- Aligning to the next cache-line boundary
This ensures vectorized memory operations can proceed safely.
310-312: LGTM! Consistent use of aligned offsets.The recv buffer pointers and tensor views now correctly use
payloadRecvBufferOffsetsto ensure each payload buffer starts at a cache-line aligned address. This is consistent with the alignment strategy and prevents misaligned access.Also applies to: 330-333
368-370: LGTM! Consistent alignment validation.The 16-byte alignment check for the payload is consistent with the dispatch operation and appropriate for external tensors used in vectorized operations.
264-265: The workspace pointer alignment check is valid.The runtime check validates that
rankWorkSpacePtris 128-byte aligned, which is guaranteed by the underlying memory allocation. MnnvlMemory allocates memory withrank_stridecalculated as a multiple offabric_page_size(512 MB), making it inherently 128-byte aligned. SincerankWorkSpacePtr = workspacePtr + epRank * workspace.stride(0)andstride(0) = rank_stride, the alignment check will always pass.
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…ons in NVLinkOneSided A2A. Signed-off-by: Bo Li <22713281+bobboli@users.noreply.github.com>
… in the A2A kernel. Signed-off-by: Bo Li <22713281+bobboli@users.noreply.github.com>
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run [--reuse-test (optional)pipeline-id --disable-fail-fast --skip-test --stage-list "A10-PyTorch-1, xxx" --gpu-type "A30, H100_PCIe" --test-backend "pytorch, cpp" --add-multi-gpu-test --only-multi-gpu-test --disable-multi-gpu-test --post-merge --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx" --detailed-log --debug(experimental)]Launch build/test pipelines. All previously running jobs will be killed.
--reuse-test (optional)pipeline-id(OPTIONAL) : Allow the new pipeline to reuse build artifacts and skip successful test stages from a specified pipeline or the last pipeline if no pipeline-id is indicated. If the Git commit ID has changed, this option will be always ignored. The DEFAULT behavior of the bot is to reuse build artifacts and successful test results from the last pipeline.--disable-reuse-test(OPTIONAL) : Explicitly prevent the pipeline from reusing build artifacts and skipping successful test stages from a previous pipeline. Ensure that all builds and tests are run regardless of previous successes.--disable-fail-fast(OPTIONAL) : Disable fail fast on build/tests/infra failures.--skip-test(OPTIONAL) : Skip all test stages, but still run build stages, package stages and sanity check stages. Note: Does NOT update GitHub check status.--stage-list "A10-PyTorch-1, xxx"(OPTIONAL) : Only run the specified test stages. Examples: "A10-PyTorch-1, xxx". Note: Does NOT update GitHub check status.--gpu-type "A30, H100_PCIe"(OPTIONAL) : Only run the test stages on the specified GPU types. Examples: "A30, H100_PCIe". Note: Does NOT update GitHub check status.--test-backend "pytorch, cpp"(OPTIONAL) : Skip test stages which don't match the specified backends. Only support [pytorch, cpp, tensorrt, triton]. Examples: "pytorch, cpp" (does not run test stages with tensorrt or triton backend). Note: Does NOT update GitHub pipeline status.--only-multi-gpu-test(OPTIONAL) : Only run the multi-GPU tests. Note: Does NOT update GitHub check status.--disable-multi-gpu-test(OPTIONAL) : Disable the multi-GPU tests. Note: Does NOT update GitHub check status.--add-multi-gpu-test(OPTIONAL) : Force run the multi-GPU tests in addition to running L0 pre-merge pipeline.--post-merge(OPTIONAL) : Run the L0 post-merge pipeline instead of the ordinary L0 pre-merge pipeline.--extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx"(OPTIONAL) : Run the ordinary L0 pre-merge pipeline and specified test stages. Examples: --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx".--detailed-log(OPTIONAL) : Enable flushing out all logs to the Jenkins console. This will significantly increase the log volume and may slow down the job.--debug(OPTIONAL) : Experimental feature. Enable access to the CI container for debugging purpose. Note: Specify exactly one stage in thestage-listparameter to access the appropriate container environment. Note: Does NOT update GitHub check status.For guidance on mapping tests to stage names, see
docs/source/reference/ci-overview.mdand the
scripts/test_to_stage_mapping.pyhelper.kill
killKill all running builds associated with pull request.
skip
skip --comment COMMENTSkip testing for latest commit on pull request.
--comment "Reason for skipping build/test"is required. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.reuse-pipeline
reuse-pipelineReuse a previous pipeline to validate current commit. This action will also kill all currently running builds associated with the pull request. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.