[None][fix] nccl symmetric with graceful fallbacks

[nv-lschneider]

Summary by CodeRabbit

Release Notes

• Bug Fixes & Improvements
  • Enhanced NCCL window buffer allocation with better handling during GPU graph capture operations
  • Improved error handling with graceful fallbacks when buffer allocation fails
  • Added warnings to guide users when optimal buffer configurations are unavailable, ensuring operations continue with alternate paths

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Description

This makes NCCL_SYMMETRIC more gracful.
If a problem occurs during creation of registered tensors, the unregistered NCCL operation will be performed.

New is also that it detects execution during graph capture, since it is not possible to register buffers during graph capture.
In a follow up PR, I will add that buffers are registered before any graph capture.
This PR only fixes bad behavior that may happen with a graceful behavior that may compromise performance (not worse the NCCL though.)

Test Coverage

Covered by existing tests.

PR Checklist

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• PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

• PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

• Test cases are provided for new code paths (see test instructions)

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• CODEOWNERS updated if ownership changes

• Documentation updated as needed

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• Please check this after reviewing the above items as appropriate for this PR.

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[coderabbitai]

📝 Walkthrough

Walkthrough

The changes introduce CUDA graph capture awareness to the NCCL window buffer allocation system. When allocating buffers, the code now checks if the current CUDA stream is in capture state; if so, it returns an empty buffer to avoid allocation during capture. The changes also add error handling and fallback mechanisms for symmetric window buffer creation in the AllReduce operation, gracefully degrading to input buffers when window buffers are unavailable.

Changes

Cohort / File(s)	Summary
NCCL Window Buffer Allocation cpp/tensorrt_llm/common/ncclUtils.cpp, cpp/tensorrt_llm/common/ncclUtils.h	Added CUDA headers and capture-state checking logic. In ncclUtils.cpp, buffer allocation now detects active CUDA graph capture and returns empty buffers when capturing. In ncclUtils.h, createNCCLWindowTensor wrapped in try/catch to handle exceptions and invalid buffers gracefully, returning empty/invalid buffers instead of throwing.
NCCL AllReduce Operation cpp/tensorrt_llm/thop/allreduceOp.cpp	Modified AllreduceOp.runNCCLAllReduceSymmetric to validate window buffers before use and conditionally create symmetric window buffers only when existing buffers are unavailable and size exceeds threshold. Added fallback logic to use input/output tensors directly when symmetric buffer creation fails, with warnings logged for each fallback case.

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~25 minutes

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (2 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title '[None][fix] nccl symmetric with graceful fallbacks' directly relates to the main changes: adding graceful fallback behavior and CUDA graph capture detection to NCCL symmetric operations.
Description check	✅ Passed	The PR description explains the rationale and changes but is quite brief. However, it covers the key aspects: graceful fallback on buffer registration failure, CUDA graph capture detection, test coverage claim, and checklist confirmation.

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✨ Finishing touches

• 📝 Generate docstrings

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[nv-lschneider]

@coderabitai review

[coderabbitai]

Actionable comments posted: 0

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (4)

cpp/tensorrt_llm/common/ncclUtils.h (1)

1-3: Update the NVIDIA copyright year to reflect 2026.

This file was modified in this PR, but the header still lists 2025. Please bump the year to 2026 (or 2025–2026) to reflect the latest meaningful modification. As per coding guidelines, please keep the header year current.

🔧 Suggested update

- * Copyright (c) 2025, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2025-2026, NVIDIA CORPORATION.  All rights reserved.

cpp/tensorrt_llm/common/ncclUtils.cpp (1)

1-3: Update the NVIDIA copyright year to reflect 2026.

This file was modified in this PR, but the header still lists 2025. Please bump the year to 2026 (or 2025–2026) to reflect the latest meaningful modification. As per coding guidelines, please keep the header year current.

🔧 Suggested update

- * Copyright (c) 2025, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2025-2026, NVIDIA CORPORATION.  All rights reserved.

cpp/tensorrt_llm/thop/allreduceOp.cpp (2)

1-4: Update the SPDX copyright range to include 2026.

This file was modified in this PR, but the header ends at 2024. Please update the range to include 2026 to reflect the latest meaningful modification. As per coding guidelines, please keep the header year current.

🔧 Suggested update

- * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION &

---

512-551: Gate output window allocation on input registration status to prevent undefined NCCL behavior.

The current code can allocate a registered output buffer even when the input buffer is unregistered (due to size threshold or allocation failure). NCCL requires that for any collective call, either all ranks use registered buffers or all use unregistered buffers; mixing them results in undefined behavior.

Condition output window allocation on the same decision that controls input registration (i.e., whether windowBuffer0.isValid() or via a useSymmetric flag) to ensure both input and output follow the same registration path.

♻️ Example refactor

+        bool const useSymmetric = windowBuffer0.isValid();
+
+        torch::Tensor outputTensor;
+        void* outputPtr = nullptr;
+        if (useSymmetric)
+        {
+            auto [normOut, windowBuffer1] = createNCCLWindowTensor(comm, input.sizes(), input.scalar_type());
+            if (windowBuffer1.isValid())
+            {
+                outputTensor = normOut;
+                outputPtr = windowBuffer1.ptr;
+            }
+            else
+            {
+                outputTensor = torch::empty_like(inputTensor);
+                outputPtr = outputTensor.data_ptr();
+                TLLM_LOG_WARNING(
+                    "[runNCCLAllReduceSymmetric] No valid symmetric buffer available; "
+                    "using plain CUDA tensor for output");
+            }
+        }
+        else
+        {
+            outputTensor = torch::empty_like(inputTensor);
+            outputPtr = outputTensor.data_ptr();
+        }
-        // Use window-backed output buffer
-        auto [normOut, windowBuffer1] = createNCCLWindowTensor(comm, input.sizes(), input.scalar_type());
-        torch::Tensor outputTensor = windowBuffer1.isValid() ? normOut : torch::empty_like(inputTensor);
-        void* outputPtr = windowBuffer1.isValid() ? windowBuffer1.ptr : outputTensor.data_ptr();
-        if (!windowBuffer1.isValid())
-        {
-            TLLM_LOG_WARNING(
-                "[runNCCLAllReduceSymmetric] No valid symmetric buffer available; "
-                "using plain CUDA tensor for output");
-        }

Also applies to: 562–569

[nv-lschneider]

/bot run --disable-fail-fast --add-multi-gpu-test

[tensorrt-cicd]

PR_Github #33778 [ run ] triggered by Bot. Commit: b1e932d

[hyukn]

I guess there might be no coverage in today's tests for NCCL_SYMMETRIC_PATH. Because #10463 has a very simple change. Do you think it will be better to combine them to get more feedback quickly from CI on this PR?

[tensorrt-cicd]

PR_Github #33778 [ run ] completed with state SUCCESS. Commit: b1e932d
/LLM/main/L0_MergeRequest_PR pipeline #26051 completed with status: 'FAILURE'

⚠️ Action Required:

• Please check the failed tests and fix your PR
• If you cannot view the failures, ask the CI triggerer to share details
• Once fixed, request an NVIDIA team member to trigger CI again

[nv-lschneider]

I added the activation of NCCL_SYMMETRIC in autotuning for better test coverage.
CI for #10463 was green at some point before rebase, so that should be OK to merge with this one too.

[nv-lschneider]

/bot run --disable-fail-fast --add-multi-gpu-test

[tensorrt-cicd]

PR_Github #33803 [ run ] triggered by Bot. Commit: 0529e4c

[tensorrt-cicd]

PR_Github #33803 [ run ] completed with state SUCCESS. Commit: 0529e4c
/LLM/main/L0_MergeRequest_PR pipeline #26071 completed with status: 'FAILURE'

⚠️ Action Required:

• Please check the failed tests and fix your PR
• If you cannot view the failures, ask the CI triggerer to share details
• Once fixed, request an NVIDIA team member to trigger CI again

[nv-lschneider]

/bot run --disable-fail-fast --add-multi-gpu-test

[tensorrt-cicd]

PR_Github #33891 [ run ] triggered by Bot. Commit: 0529e4c

[tensorrt-cicd]

PR_Github #33891 [ run ] completed with state FAILURE. Commit: 0529e4c

[nv-lschneider]

/bot run --disable-fail-fast --add-multi-gpu-test

[tensorrt-cicd]

PR_Github #33894 [ run ] triggered by Bot. Commit: 0529e4c

[tensorrt-cicd]

PR_Github #33894 [ run ] completed with state SUCCESS. Commit: 0529e4c
/LLM/main/L0_MergeRequest_PR pipeline #26142 completed with status: 'FAILURE'

⚠️ Action Required:

• Please check the failed tests and fix your PR
• If you cannot view the failures, ask the CI triggerer to share details
• Once fixed, request an NVIDIA team member to trigger CI again

[nv-lschneider]

/bot run --disable-fail-fast --add-multi-gpu-test

[tensorrt-cicd]

PR_Github #33920 [ run ] triggered by Bot. Commit: 0529e4c

[tensorrt-cicd]

PR_Github #33920 [ run ] completed with state SUCCESS. Commit: 0529e4c
/LLM/main/L0_MergeRequest_PR pipeline #26160 completed with status: 'SUCCESS'

[Tabrizian]

I think this test needs to be unwaived too:

TensorRT-LLM/tests/integration/test_lists/waives.txt

Line 301 in 393c3d2

accuracy/test_llm_api_pytorch.py::TestDeepSeekR1::test_nvfp4_multi_gpus[latency] SKIP (https://nvbugs/5814309)

[hyukn]

Hi @nv-lschneider. Thanks for the effort. I noticed that the last failed CI before the final successful one hits this test

_torch/auto_deploy/unit/multigpu/transformations/library/test_allreduce_residual_rmsnorm_fusion.py FAILED [ 24%]

I am not sure if it could be a flaky one.

[nv-lschneider]

Hi @nv-lschneider. Thanks for the effort. I noticed that the last failed CI before the final successful one hits this test

_torch/auto_deploy/unit/multigpu/transformations/library/test_allreduce_residual_rmsnorm_fusion.py FAILED [ 24%]

I am not sure if it could be a flaky one.

Thanks for pointing that out.
I ran the test locally about 20 times on GB200 and did not notice any failure.
So at least on that hardware it does not seem very flaky to me.