Don't use ZR as target in LSE atomics

[EgorBo]

Addresses @AndyAyersMS's concerns in #105441 (comment)

TL;DR - some instructions relax their semantics when ZR register is used as target. LLVM avoids that via atomicBarrierDroppedOnZero and atomicBarrierDroppedOnZero

[EgorBo]

@AndyAyersMS @dotnet/jit-contrib cc @VSadov PTAL, no diffs. I am not sure LSRA can ever decide to assign a zero reg as target reg so my availableIntRegs & ~(SRBM_ZR) is likely unnecessary (UPD: removed). But what used to be possible is that LSRA could assign REG_NA for target (when it's unused) and the codegen used ZR reg to discard the result.

[AndyAyersMS]

Seems like we might need more of this elsewhere?

[EgorBo]

Seems like we might need more of this elsewhere?

Can you please point me to any? There is one more place with INS_casal* but it's not affected by ZR.

[AndyAyersMS]

Seems like we might need more of this elsewhere?

Can you please point me to any? There is one more place with INS_casal* but it's not affected by ZR.

I don't know of any -- just that LLVM has relatively large lists for both cases.

[EgorBo]

just that LLVM has relatively large lists for both cases.

Yeah the list of instructions is big, but we don't use any besides these in my PR. Arm64 has many interesting atomic instructions like "atomic min/max, atomic bit-clear/bit-set" but .NET doesn't have APIs for them/doesn't try to recognize idioms