Adding zmmStateSupport and AVX512F, AVX512CD, AVX512BW, AVX512DQ and AVX512VL ISAs.

[DeepakRajendrakumaran]

This change adds logic for detecting avx512 support via zmmStateSupport and the logic in EEJitManager::SetCpuInfo()

For specifics of zmmStateSupport- see section 15.2 DETECTION OF AVX-512 FOUNDATION INSTRUCTIONS in Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 for details. 14.3 DETECTION OF AVX INSTRUCTIONS details logic used for AVX and SSE.

The other changes are to add new AVX512 ISAs. Most of these changes are autogenerated code via src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt

[ghost]

I couldn't figure out the best area label to add to this PR. If you have write-permissions please help me learn by adding exactly one area label.

[DeepakRajendrakumaran]

@BruceForstall @davidwrighton

[DeepakRajendrakumaran]

@tannergooding I cannot figure out where/how XmmYmmStateSupport in src/coreclr/pal/src/arch/amd64/processor.cpp is used. And why it's XmmYmmStateSupport as opposed to xmmYmmStateSupport . Are you familiar with this call?

[tannergooding]

I cannot figure out where/how XmmYmmStateSupport in src/coreclr/pal/src/arch/amd64/processor.cpp is used. And why it's XmmYmmStateSupport as opposed to xmmYmmStateSupport . Are you familiar with this call?

I don't see any existing consumers, it might be dead code.

[tannergooding]

There's still a couple of pending comments above and we need to revise the JIT/EE Version Guid here: https://github.com/dotnet/runtime/blob/main/src/coreclr/inc/jiteeversionguid.h

Otherwise the changes look good/correct to me and I think we can adjust the _VL handling if needed later. Would still be good if someone from @dotnet/crossgen-contrib could review those changes as well, however.

[DeepakRajendrakumaran]

There's still a couple of pending comments above and we need to revise the JIT/EE Version Guid here: https://github.com/dotnet/runtime/blob/main/src/coreclr/inc/jiteeversionguid.h

Otherwise the changes look good/correct to me and I think we can adjust the _VL handling if needed later. Would still be good if someone from @dotnet/crossgen-contrib could review those changes as well, however.

Have added the requested changes.

[BruceForstall]

Tagging the group... just to see it work... @dotnet/avx512-contrib

[DeepakRajendrakumaran]

Tagging the group... just to see it work... @dotnet/avx512-contrib

Works for me. Got an email notification

[DeepakRajendrakumaran]

There's still a couple of pending comments above and we need to revise the JIT/EE Version Guid here: https://github.com/dotnet/runtime/blob/main/src/coreclr/inc/jiteeversionguid.h

Otherwise the changes look good/correct to me and I think we can adjust the _VL handling if needed later. Would still be good if someone from @dotnet/crossgen-contrib could review those changes as well, however.

@tannergooding I had originally missed your comment re JIT/EE Version Guid. I have updated it now following instruction in the file(ran "uuidgen.exe -s" locally and replaced the GUID in file with that). Please let me know if there is anything else needed from us to push this forward.

[davidwrighton]

I've approved, but I'd like to see an approval from @tannergooding as well before we merge.

[tannergooding]

LGTM, minus the question about the NAOT instruction set names

[jkotas]

This needs to be hooked up here:

runtime/src/coreclr/nativeaot/Runtime/startup.cpp

Line 166 in 0a60d95

bool DetectCPUFeatures()

[tannergooding]

Looks like the AVX512 ISA checks need to be mirrored there as well.

[DeepakRajendrakumaran]

And the 'end' was in the wrong place :) . Have added the checks in startup.cpp

[tannergooding]

Failures are #75667

super-pmi failures are due to the JIT/EE version guid update

timeouts are on a subset of arm/arm64 machines and are happening everywhere, this change is explicitly around xarch.