ARM64-SVE: Implement IF_SVE_BV_2A#99049

a74nh · 2024-02-28T14:54:16Z

Part of #94549. Adds IF_SVE_BV_2A, IF_SVE_BV_2A_A and IF_SVE_BV_2A_J.

coreclr:

mov z15.b, p5/z, #0
mov z5.b, p15/z, #27
mov z31.b, p0/z, #-128
mov z0.b, p5/z, #127
mov z15.h, p5/z, #0
mov z23.s, p12/z, #10
mov z4.d, p0/z, #-128
mov z19.h, p15/z, #127
mov z1.s, p0/z, #1, LSL #8
mov z1.d, p0/z, #12, LSL #8
mov z1.h, p0/z, #-12, LSL #8
mov z1.s, p0/z, #-128, LSL #8
mov z0.d, p0/z, #127, LSL #8
mov z1.b, p12/m, #5
mov z27.h, p13/m, #22, LSL #8
mov z27.h, p13/m, #-22, LSL #8

Capstone

0F001505  mov   z15.b, p5/z, #0
65031F05  mov   z5.b, p15/z, #0x1B
1F101005  mov   z31.b, p0/z, #-0x80
E00F1505  mov   z0.b, p5/z, #0x7F
0F005505  mov   z15.h, p5/z, #0
57019C05  mov   z23.s, p12/z, #0xA
0410D005  mov   z4.d, p0/z, #0x80
F30F5F05  mov   z19.h, p15/z, #0x7F
21209005  mov   z1.s, p0/z, #0x100
8121D005  mov   z1.d, p0/z, #0xC00
813E5005  mov   z1.h, p0/z, #-0xC00
01309005  mov   z1.s, p0/z, #0x8000
E02FD005  mov   z0.d, p0/z, #0x7F00
A1401C05  mov   z1.b, p12/m, #5
DB625D05  mov   z27.h, p13/m, #0x1600
5B7D5D05  mov   z27.h, p13/m, #-0x1600

Ignoring the differences in immediate formatting (decimal + shift vs hex), there are two errors with -ve numbers in coreclr being positive in capstone

To check this, I ran in gdb and got:

   0x0000ffffa98b394c:	mov	z15.b, p5/z, #0
   0x0000ffffa98b3950:	mov	z5.b, p15/z, #27
   0x0000ffffa98b3954:	mov	z31.b, p0/z, #-128
   0x0000ffffa98b3958:	mov	z0.b, p5/z, #127
   0x0000ffffa98b395c:	mov	z15.h, p5/z, #0
   0x0000ffffa98b3960:	mov	z23.s, p12/z, #10
   0x0000ffffa98b3964:	mov	z4.d, p0/z, #-128
   0x0000ffffa98b3968:	mov	z19.h, p15/z, #127
   0x0000ffffa98b396c:	mov	z1.s, p0/z, #256
   0x0000ffffa98b3970:	mov	z1.d, p0/z, #3072
   0x0000ffffa98b3974:	mov	z1.h, p0/z, #-3072
   0x0000ffffa98b3978:	mov	z1.s, p0/z, #-32768
   0x0000ffffa98b397c:	mov	z0.d, p0/z, #32512
   0x0000ffffa98b3980:	mov	z1.b, p12/m, #5
   0x0000ffffa98b3984:	mov	z27.h, p13/m, #5632
   0x0000ffffa98b3988:	mov	z27.h, p13/m, #-5632

In summary:

coreclr:     mov z4.d, p0/z, #-128
capstone: mov   z4.d, p0/z, #0x80
gdb:          mov	z4.d, p0/z, #-128

coreclr :    mov z1.s, p0/z, #-128, LSL #8
capstone: mov   z1.s, p0/z, #0x8000
gdb:          mov	z1.s, p0/z, #-32768

I'm happy this is an error in capstone and that coreclr+gdb are correct.

ghost · 2024-02-28T14:54:26Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

Part of #94549. Adds IF_SVE_BV_2A, IF_SVE_BV_2A_A and IF_SVE_BV_2A_J.

coreclr:

mov z15.b, p5/z, #0
mov z5.b, p15/z, #27
mov z31.b, p0/z, #-128
mov z0.b, p5/z, #127
mov z15.h, p5/z, #0
mov z23.s, p12/z, #10
mov z4.d, p0/z, #-128
mov z19.h, p15/z, #127
mov z1.s, p0/z, #1, LSL #8
mov z1.d, p0/z, #12, LSL #8
mov z1.h, p0/z, #-12, LSL #8
mov z1.s, p0/z, #-128, LSL #8
mov z0.d, p0/z, #127, LSL #8
mov z1.b, p12/m, #5
mov z27.h, p13/m, #22, LSL #8
mov z27.h, p13/m, #-22, LSL #8

Capstone

0F001505  mov   z15.b, p5/z, #0
65031F05  mov   z5.b, p15/z, #0x1B
1F101005  mov   z31.b, p0/z, #-0x80
E00F1505  mov   z0.b, p5/z, #0x7F
0F005505  mov   z15.h, p5/z, #0
57019C05  mov   z23.s, p12/z, #0xA
0410D005  mov   z4.d, p0/z, #0x80
F30F5F05  mov   z19.h, p15/z, #0x7F
21209005  mov   z1.s, p0/z, #0x100
8121D005  mov   z1.d, p0/z, #0xC00
813E5005  mov   z1.h, p0/z, #-0xC00
01309005  mov   z1.s, p0/z, #0x8000
E02FD005  mov   z0.d, p0/z, #0x7F00
A1401C05  mov   z1.b, p12/m, #5
DB625D05  mov   z27.h, p13/m, #0x1600
5B7D5D05  mov   z27.h, p13/m, #-0x1600

Ignoring the differences in immediate formatting (decimal + shift vs hex), there are two errors with -ve numbers in coreclr being positive in capstone

To check this, I ran in gdb and got:

   0x0000ffffa98b394c:	mov	z15.b, p5/z, #0
   0x0000ffffa98b3950:	mov	z5.b, p15/z, #27
   0x0000ffffa98b3954:	mov	z31.b, p0/z, #-128
   0x0000ffffa98b3958:	mov	z0.b, p5/z, #127
   0x0000ffffa98b395c:	mov	z15.h, p5/z, #0
   0x0000ffffa98b3960:	mov	z23.s, p12/z, #10
   0x0000ffffa98b3964:	mov	z4.d, p0/z, #-128
   0x0000ffffa98b3968:	mov	z19.h, p15/z, #127
   0x0000ffffa98b396c:	mov	z1.s, p0/z, #256
   0x0000ffffa98b3970:	mov	z1.d, p0/z, #3072
   0x0000ffffa98b3974:	mov	z1.h, p0/z, #-3072
   0x0000ffffa98b3978:	mov	z1.s, p0/z, #-32768
   0x0000ffffa98b397c:	mov	z0.d, p0/z, #32512
   0x0000ffffa98b3980:	mov	z1.b, p12/m, #5
   0x0000ffffa98b3984:	mov	z27.h, p13/m, #5632
   0x0000ffffa98b3988:	mov	z27.h, p13/m, #-5632

In summary:

coreclr:     mov z4.d, p0/z, #-128
capstone: mov   z4.d, p0/z, #0x80
gdb:          mov	z4.d, p0/z, #-128

coreclr :    mov z1.s, p0/z, #-128, LSL #8
capstone: mov   z1.s, p0/z, #0x8000
gdb:          mov	z1.s, p0/z, #-32768

I'm happy this is an error in capstone and that coreclr+gdb are correct.

Author:	a74nh
Assignees:	-
Labels:	`area-CodeGen-coreclr`
Milestone:	-

a74nh · 2024-02-28T14:55:47Z

@dotnet/jit-contrib @dotnet/arm64-contrib @a74nh @kunalspathak this is ready.

a74nh · 2024-02-28T14:56:59Z

Note - I wasn't due to do this, but, I needed it for #98218

amanasifkhalid

LGTM, thanks!

src/coreclr/jit/codegenarm64test.cpp

src/coreclr/jit/emitarm64.cpp

kunalspathak · 2024-03-05T00:00:07Z

src/coreclr/jit/codegenarm64test.cpp

+                              INS_OPTS_SCALABLE_D); // MOV <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>}
+
+    // IF_SVE_BV_2A_A
+    theEmitter->emitIns_R_R_I(INS_sve_cpy, EA_SCALABLE, REG_V1, REG_P12, 5, INS_OPTS_SCALABLE_B,


this should be removed I assume?

you can do it in a follow-up PR though.

ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 28, 2024

a74nh marked this pull request as ready for review February 28, 2024 14:56

ARM64-SVE: Implement IF_SVE_BV_2A

5715615

a74nh force-pushed the IF_SVE_BV_2A_github branch from 438a75e to 5715615 Compare February 28, 2024 15:01

amanasifkhalid approved these changes Feb 28, 2024

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a74nh commented Feb 28, 2024

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kunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label Feb 28, 2024

kunalspathak mentioned this pull request Feb 28, 2024

Arm64: Implement SVE encodings #94549

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build-analysis bot mentioned this pull request Feb 28, 2024

CI test failure: Connection handshake was canceled due to the configured timeout #99074

Closed

a74nh added 4 commits February 29, 2024 10:48

Add sopt assert

1404a78

Merge main

2af21f0

Merge main

e0aca4d

Remove IF_SVE_BV_2A_A handling

df49130

This was referenced Mar 1, 2024

Tracking issue for CI build timeouts #76454

Closed

slow macOS - "##[error]The job running on agent Azure Pipelines 9 ran longer than the maximum time of 60 minutes." dotnet/dnceng#1883

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1a65e97

a74nh mentioned this pull request Mar 4, 2024

JIT ARM64-SVE: Add TrueMask and LoadVector #98218

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JIT ARM64-SVE: Remove INS_SCALABLE_OPTS_SHIFT #99258

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amanasifkhalid requested a review from kunalspathak March 4, 2024 23:15

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kunalspathak merged commit 605dc6c into dotnet:main Mar 5, 2024

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ARM64-SVE: Implement IF_SVE_BV_2A#99049

ARM64-SVE: Implement IF_SVE_BV_2A#99049
kunalspathak merged 7 commits intodotnet:mainfrom
a74nh:IF_SVE_BV_2A_github

a74nh commented Feb 28, 2024

Uh oh!

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a74nh commented Feb 28, 2024

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