Add SMP support for ARM/RISC-V

[midnightveil]

This PR adds support for SMP builds of the kernel on AArch64.

We have a psci_target_cpus[] array, currently hardcoded, for the IDs of the cores to boot. This should match the values specified in the device tree /cpu@0/ node's <reg> field. Note that due to quirks of various platforms (e.g. OdroidC4), these do not (but can) match the MPIDR values that hardware reports, so we maintain a different table of their MPIDR values.

There a few TODOs scattered throughout this code.

[midnightveil]

Ping @Indanz as you had comments on the previous iteration of this code in the smp branch. This has followed your pieces of advice.

[midnightveil]

I'll add a quick note on why this was removed: this is wrong, as we are not guaranteed that the CPU we are booting on will have the Aff0 value of the MPIDR_EL1 to be 0. Nor do we expect that this part of the code should run on multiple cores. This dates back the initial public release of seL4CP.

[Ivan-Velickovic]

Once we finish the code changes we'll need to update a couple sections on the manual (e.g the list/description of Microkit configs and the QEMU sections on how to boot with multiple cores).

We'll also need to adjust the porting platform support section for the SMP related changes.

[midnightveil]

This is blocked on seL4/seL4#1563

[midnightveil]

Previous before force push cleanups: https://github.com/au-ts/microkit/tree/julia/smp-presquash

diff

diff --git a/flake.nix b/flake.nix
index 5a3f926..65a24df 100644
--- a/flake.nix
+++ b/flake.nix
@@ -96,6 +96,7 @@
             ninja
             libxml2
             qemu
+            gnutar
           ];

           # Necessary for Rust bindgen
diff --git a/loader/src/aarch64/cpus.c b/loader/src/aarch64/cpus.c
index dc76a1f..7ba31e2 100644
--- a/loader/src/aarch64/cpus.c
+++ b/loader/src/aarch64/cpus.c
@@ -24,7 +24,7 @@ size_t cpu_mpidrs[NUM_ACTIVE_CPUS];

 void plat_save_hw_id(int logical_cpu, size_t hw_id)
 {
-    cpu_mpidrs[(uint8_t)logical_cpu] = hw_id;
+    cpu_mpidrs[logical_cpu] = hw_id;
 }

 uint64_t plat_get_hw_id(int logical_cpu)
@@ -73,6 +73,9 @@ void arm_secondary_cpu_entry(int logical_cpu, uint64_t mpidr_el1)
     } else if (logical_cpu >= NUM_ACTIVE_CPUS) {
         LDR_PRINT("ERROR", logical_cpu, "secondary CPU should not be >NUM_ACTIVE_CPUS\n");
         goto fail;
+    } else if (logical_cpu < 0) {
+        LDR_PRINT("ERROR", logical_cpu, "secondary CPU should not have negative logical id\n");
+        goto fail;
     }

     plat_save_hw_id(logical_cpu, mpidr_el1);