Upstream the support for STM32WBA6#88407
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The following west manifest projects have changed revision in this Pull Request:
✅ All manifest checks OK Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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update modules hal stm32 for stm32wb and stm32wba Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds support for the STM32WBA65x MCU. Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds the Device Tree include files for the STM32WBA65x device Adding GPIO D/E/G banks. Renaming JTAG reset pin. Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the clock domain definition for the stm32wba CCIPR Signed-off-by: Francois Ramu <francois.ramu@st.com>
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Updated the west.yml with HAL STM32 merged commit f467d8e |
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| ST Nucleo WBA65RI | ||
| ################# |
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sphinx directive adds this automatically
| ST Nucleo WBA65RI | |
| ################# |
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| .. image:: img/nucleo_wba65ri.webp | ||
| :align: center | ||
| :alt: Nucleo WBA65RI |
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sphinx directive adds this automatically
| .. image:: img/nucleo_wba65ri.webp | |
| :align: center | |
| :alt: Nucleo WBA65RI |
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| &rng { | ||
| status = "okay"; | ||
| }; |
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duplicate entry
| &rng { | |
| status = "okay"; | |
| }; |
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| board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") | |||
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| board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") | |
| # SPDX-License-Identifier: Apache-2.0 | |
| board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") |
| ----------- | ||
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| Nucleo WBA65RI board has 3 U(S)ARTs. The Zephyr console output is assigned to USART1. | ||
| Default settings are 115500 8N1. |
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| Default settings are 115500 8N1. | |
| Default settings are 115200 8N1. |
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| # Note: Using OpenOCD using nucloe_wba65ri requires using openocd fork. | |||
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| # Note: Using OpenOCD using nucloe_wba65ri requires using openocd fork. | |
| # Note: Using OpenOCD using nucleo_wba65ri requires using openocd fork. |
| - I2C_1_SCL : PB2 | ||
| - I2C_1_SDA : PB1 | ||
| - USER_PB : PC13 | ||
| - LD1 : PB4 |
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this is not what devicetree says?
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Yes, it should be LD1 : PD8
Introduce the stm32WBA56 nucleo board. HSE32 divided by 2 is the source clock. Signed-off-by: Francois Ramu <francois.ramu@st.com>
-The stm32wba6x has Dual Bank memory. Change the flash driver to support this OPTion given by presence of the DUAL_BANK bit (21) in the FLASH_OPTR register. -Flash erase with 2 banks: Add the control of the BKER bit of the FLASH_NSCR1 to select BANK1 or 2 of the internal flash depending on the page number >127 for BANK2 Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add nucleo_wba65ri overlay file Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
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kartben
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thanks for addressing my comments so quickly :)
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Awesome work, very keen to use this part with Zephyr 😃 |
Enabling support for STM32WBA6