SCLive

This page contains the various SystemC tutorials found on this site and organises them into sequential chapters.

Chapter 1: Introduction

This chapter summarises the why where and what of SystemC. It also touches on additional libraries such as TLM and SCV.

Chapter 2: C++ for Hardware Modeling

This chapter discusses the validity of modeling hardware system using the C++ language. Examples of basic hardware models written in C++ are provided.

Chapter 3: Modules

This chapter introduces the use of modules in SystemC. Essential elements such as inheritance, constructors and destructors will also be covered.

Chapter 4: Ports

This chapter covers the use of ports in SystemC hardware models. This section you touch on the ports and interfaces relationship as well as ports and channels compatibility.

Chapter 5: sc_thread sc_method

This chapter examines the use of the SystemC processes namely: the sc_thread and sc_method. Processes registrations and execution will also be covered.

Chapter 6: Hierarchy

This chapter will look at the creation of hierarchical design through the composition mechanism. We will also briefly cover the use of inheritance for creating hierarchy in SystemC.

Chapter 7: Interfaces and Channels

This chapter will illustrate the processes involved in creating a user defined interface. This section will also cover ports/interfaces and channels/interfaces relationship. Furthermore this chapter will cover predefined and user defined channels both primitive and hierarchical.

Chapter 8: SCV

This chapter will introduce the principles behind the creation of SCV. Practical examples of simple randomisation and transaction recording will be given.

Chapter 9: TLM

This chapter will examine the need for a standardised Transaction Level Modeling interface and provide basic examples of blocking/non blocking, unidirectional, bi-directional interfaces.

Chapter 10: GDB and DDD

This chapter will explain how the GPL GDB or DDD can be use to provide basic debugging environments. This section will cover breakpoints, data examination and querying simulation time.