Zip CPU (@zipcpu) / X

Zip CPU

7,730 posts

Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Gisselquist Technology, LLC,

Joined January 2017

Pinned
Zip CPU
@zipcpu
Oct 4, 2018
Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!
Zip CPU
@zipcpu
10h
So ... what's causing all the pauses? If we expand the scope of the capture, we can see both controller generated and device generated pauses.
Zip CPU
@zipcpu
11h
Today's eMMC success: HS400 Enhanced. Fastest instantaneous throughput: 311MB/s reading. However, with the filesystem in place, we only see 5.8MB/s writing and 42.7 MB/s reading
Zip CPU
@zipcpu
11h
Today's eMMC success: HS400 Enhanced. Fastest instantaneous throughput: 311MB/s reading. However, with the filesystem in place, we only see 5.8MB/s writing and 42.7 MB/s reading
Zip CPU
@zipcpu
Jul 30
Ok, solved the problem of the mystery pause ... my filesystem is only writing 16 sectors at a time. Between every set of 16 sectors, there's a pause ... so that must be the software time required to prepare another DMA transfer. Therefore, this pause is software caused, not IP
Zip CPU
@zipcpu
Jul 30
Making a lot of progress at eMMC HS200. With the filesystem in the way, I can achieve 5.5MB/s write and 28.7MB/s reads.
Zip CPU
@zipcpu
Jul 30
Making a lot of progress at eMMC HS200. With the filesystem in the way, I can achieve 5.5MB/s write and 28.7MB/s reads.
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