Hexagon inline asm: add reg_pair, vreg, vreg_pair, and qreg register classes

[androm3da]

Add three new register classes for the Hexagon inline assembly backend:

• reg_pair: GPR double registers (r1:0 through r27:26)
• vreg: HVX vector registers (v0-v31)
• qreg: HVX predicate registers (q0-q3), clobber-only for now

[rustbot]

r? @chenyukang

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[rustbot]

Some changes occurred in compiler/rustc_codegen_gcc

cc @antoyo, @GuillaumeGomez

[chenyukang]

@rustbot reroll

[androm3da]

cc @quic-mliebel

[JohnTitor]

Looks good, could you squash fixup commits?

[androm3da]

Looks good, could you squash fixup commits?

done, thanks

[quic-mliebel]

Should named register pairs work for input/output?

When using any of the non-blocked register pairs they get rejected:

error: couldn't allocate input reg for constraint '{r3:2}'
--> /tmp/test_regpair.rs:14:11
     |
14 |     asm!("nop", in("r3:2") x);
     |           ^^^

error: couldn't allocate output register for constraint '{r3:2}'
--> /tmp/test_regpair.rs:27:11
     |
27 |     asm!("nop", lateout("r3:2") y);
     |           ^^^

error: couldn't allocate output register for constraint '{r3:2}'
--> /tmp/test_regpair.rs:20:11
     |
20 |     asm!("nop", out("r3:2") y);
     |           ^^^

error: aborting due to 3 previous errors

[androm3da]

Should named register pairs work for input/output?

Good catch. Fixed. TBH I didn't know this inline asm feature existed.

Also improved the test coverage.

[androm3da]

I left out a file by mistake from the previous commit.

While reviewing the omitted file I also noticed that we can/should support vreg pairs in this update. So the update in aa9da4b now includes support for those.

[quic-mliebel]

LGTM 👍

[JohnTitor]

Thank you both! @bors r+

View changes since this review

[rust-bors]

📌 Commit aa9da4b has been approved by JohnTitor

It is now in the queue for this repository.