[X86] Account for domain crossing penalties in the scheduling of SSE/AVX instructions

[RKSimon]

Bugzilla Link	32487
Version	trunk
OS	All
Blocks	#31672
CC	@adibiagio,@legrosbuffle,@gchatelet,@LebedevRI

Extended Description

X86 domain crossing penalties are a lot more complicated than we account for, each CPUs treat instructions from the same domain quite differently. We should be trying to better model this to allow instruction selection to better tune for particular CPUs.

[RKSimon]

This will probably need to be done through ReadAdvance entries somehow, it should be possible to do this for forwarding between resources as well (e.g. 1cy penalty for fp-add to vec-imul etc.).