[X86] VPERMI2W/VPERMT2W port assignment in SKX scheduler model disagrees with IACA

[topperc]

Bugzilla Link	35714
Resolution	INVALID
Resolved on	Dec 21, 2017 09:15
Version	trunk
OS	All
Blocks	#31672
CC	@RKSimon

Extended Description

The scheduler model shows one uop on port 0/1/5 and two on port 5. But IACA says its one port 0 uop and two port 5 uops. I don't know which is correct.

def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2Wrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMT2W128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMT2W256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMT2Wrr(b?)(k?)(z?)")>;

[topperc]

Ok maybe I just don't know how to read IACA's output. And I only looked because of what this spreadsheet said about it http://users.atw.hu/instlatx64/AVX512_SKX_PortAssign_v102_PUB.ods