[X86] Scheduler information for FXRSTOR on Sandybridge looks bogus

[topperc]

Bugzilla Link	35956
Version	trunk
OS	All
Blocks	#31672
CC	@RKSimon

Extended Description

I highly doubt this is correct. Every other scheduler model shows an order of magnitude more uops and instructions.

def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 5;
let NumMicroOps = 5;
let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;

[topperc]

mentioned in issue llvm/llvm-bugzilla-archive#35979