[X86] SkylakeClient scheduler model doesn't know that client has less vector ALUs than server

[topperc]

Bugzilla Link	36827
Resolution	FIXED
Resolved on	Aug 18, 2021 03:58
Version	trunk
OS	Windows NT
Blocks	#31672
CC	@legrosbuffle,@gchatelet,@RKSimon
Fixed by commit(s)	58afb4e

Extended Description

For example, skylake client only has 2 vector mutltipliers on ports 0 and 1. But we have this in the scheduler model.

def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQrr")>;

[topperc]

There's also only 2 add units on client and 3 on server. We get this correct in the scheduler models.

[RKSimon]

These specific cases were fixed back in rG58afb4ea584e.

Ideally we need someone to run llvm-exegesis on various skylake (and derivative) hardware to identify any other discrepancies.