[X86] SLM/Sandy Models don't account for load latency for SSE42/AES/CLMUL classes

[RKSimon]

Bugzilla Link	36894
Resolution	FIXED
Resolved on	Feb 05, 2020 04:12
Version	trunk
OS	Windows NT
Blocks	#31672
CC	@topperc
Fixed by commit(s)	rGf25a2a3de5b5,rG8616bd417f7a

Extended Description

e.g.

def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
let Latency = 10;
let ResourceCycles = [10];
}
def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 10;
let ResourceCycles = [10, 1];
}

I'd expect the WriteCLMulLd Latency to at least be 13cy (default LoadLat), same for the others.

[RKSimon]

SandyBridge has missed a few cases as well:

e.g.

def : WriteRes<WritePCmpEStrI, [SBPort015]> {
let Latency = 4;
let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
let Latency = 4;
let ResourceCycles = [7, 1];
}

[RKSimon]

SLM fixes - rGf25a2a3de5b5

[RKSimon]

SandyBridge fixes - rG8616bd417f7a