[X86] Skylake server/client models do not declare zeroing idioms

[llvmbot]

Bugzilla Link	41982
Version	trunk
OS	All
Blocks	#31672
Reporter	LLVM Bugzilla Contributor
CC	@adibiagio,@legrosbuffle,@topperc,@RKSimon,@MattPD,@rotateright

Extended Description

This seems similar: #36019

It was marked fixed, but llvm-mca is still not recognizing xor as a zeroing idiom in this simple test case. Note that the second divl has to wait for the first to finish, despite the outputs being zeroed.

~ ❯❯❯ cat asm.s
	xorl %eax, %eax
	xorl %edx, %edx
	divl %edi
~ ❯❯❯ ~/clangmr/bin/llvm-mca -timeline -timeline-max-cycles=200  ~/asm.s                                                                                                                    ✘ 130 
<snip>


Timeline view:
                    0123456789          0123456789          0123456789          0123456789          0123456789          0123456789          0123456789          0123456789  
Index     0123456789          0123456789          0123456789          0123456789          0123456789          0123456789          0123456789          0123456789          01

[0,0]     DeER .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    ..   xorl	%eax, %eax
[0,1]     DeER .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    ..   xorl	%edx, %edx
[0,2]     .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER.    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    ..   divl	%edi
[1,0]     .    .D=======================================================================eER    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    ..   xorl	%eax, %eax
[1,1]     .    .D=======================================================================eER    .    .    .    .    .    .    .    .    .    .    .    .    .    .    .    ..   xorl	%edx, %edx
[1,2]     .    . D=======================================================================eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER   ..   divl	%edi
[2,0]     .    .    . D==============================================================================================================================================eER  ..   xorl	%eax, %eax
[2,1]     .    .    . D==============================================================================================================================================eER  ..   xorl	%edx, %edx

[topperc]

Xor isn't a dependency breaking idiom on all CPUs. Is llvm-mca using a generic scheduler there or a specific CPU?

Also on most CPUs divides can't overlap. The division operation iterates through the same circuit in a loop basically doing shifts and subtracts. Not sure if we model that correctly on all CPUs.

[RKSimon]

Brennan - what CPU are you targetting? You just raised [Bug #​41983] where it mentions SkylakeServer?

[llvmbot]

Craig, thanks for the comment.

llvm-mca there is using the Skylake-X scheduler, which should definitely support zeroing idioms.

As for your second point, when I break the dependency by manually writing something into the registers, the divs do overlap: https://pastebin.com/raw/D6GxXNRe

[llvmbot]

Simon I am a bit confused by the terminology, but I think Skylake-X, Skylake Server, and Skylake-AVX512 are the same thing, and I am targeting that. Please correct me if I'm wrong.

At any rate, I get the same results when I pass -mcpu=skylake-avx512.

[llvmbot]

Proof that divs can overlap

[adibiagio]

If no mcpu flag is specified, then llvm-mca defaults to "native" processor.

llvm-mca is able to recognize zero idiom instructions.
However, not all processor models describe how to identify zero idiom instructions. That can be done using a specific tablegen syntax (by instantiating class IsZeroIdiomFunction).

As far as I am aware of, only Btver2 (AMD Jaguar) and Bdver2 (AMD Piledriver) currently describe dependency breaking instructions (in particular zero-idioms) via tablegen.

So, if you are simulating an Intel processor, chances are that information about zero-idioms is missing in the associated scheduling model

[llvmbot]

Full output of xor version showing the bug

[RKSimon]

This is a x86 backend issue - llvm-mca will use zero-idioms if the model declares it.

We added zero-idiom patterns to Jaguar (btver2) and Piledriver (bdver2) models, the Intel models just need to do something similar for the instructions they support.

[llvmbot]

Andrea and Simon, Thank you for the information.

Do you think we should change the name of this bug to "Intel scheduling models do not understand xor to be a zeroing idiom" ?

I think it is definitely a real problem, even if the culprit is not llvm-mca.

[adibiagio]

Thanks for updating the bugzilla title.

It is indeed a problem. Dependency breaking instructions and optimizable moves are quite common. That's why in the past I decided to add a framework to describe those.

It would be really nice if somebody could contribute that missing information for most Intel processors.

[topperc]

Candidate patch https://reviews.llvm.org/D62360

[boomanaiden154]

It looks like this got fixed in 6eb8fc9.