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RISC-V
The Open-Standard Instruction Set Architecture
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- Zurich, CH
- https://riscv.org
- @risc_v
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- riscv-cheri Public
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
riscv/riscv-cheri’s past year of commit activity - riscv-docs-base-container-image Public
A base container image populated with the dependencies to build the RISC-V Documentation.
riscv/riscv-docs-base-container-image’s past year of commit activity - riscv-zabha Public
The Zabha extension provides support for byte and halfword atomic memory operations.
riscv/riscv-zabha’s past year of commit activity - composable-custom-extensions Public
This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
riscv/composable-custom-extensions’s past year of commit activity - sig-functional-safety-whitepaper Public
GitHub repository for the Functional Safety SIG Whitepaper Development
riscv/sig-functional-safety-whitepaper’s past year of commit activity - docs-spec-template Public template
riscv/docs-spec-template’s past year of commit activity
