Cores, IP, and standards
The OpenHW Foundation curates a family of permissively licensed, open-source, industrial-grade RISC-V cores, verification suites, and software tools developed collaboratively by a global hardware engineering community. Each project is hosted in its own dedicated GitHub repository. The RTL of each repository is highly configurable into multiple unique cores.
CORE-ET combines many-core RISC-V-based RTL with MRAM, creating a basis for the ET Silicon Platform (ETSP). CORE-ET can be deployed in a traditional configuration with the host CPU accessing ETSP as an Intelligent RAM via Hyperbus OR as a self-hosted array of microcontrollers (with or without a host CPU).
CVA6
The CVA6 project is a highly configurable, production quality, 6-stage RISC-V core for application and embedded class applications. The CVA6 targets ASIC implementations, and ranges from embedded 32 bit configurations all the way to Application ready 64 bit versions.
CVW
CVW (CV-Wally) is a configurable 32-bit and 64-bit RISC-V core with a 5-stage pipeline, support for A, B, C, D, F, M, Q, and Zk* extensions, and optional caches, branch prediction, virtual memory, AHB, RAMs, and peripherals. Wally is primarily targeted at education but ready for industrial use thanks to an extensive UVM Verification Framework. CV-Wally is accompanied by a textbook, hands-on tutorials, and an engineering course.
CV-X-IF
The CORE-V eXtension interface (CV-X-IF) is a RISC-V eXtension interface that provides a generalized framework suitable to implement custom co-processors and ISA extensions for existing RISC-V processors. It features independent channels for accelerator-agnostic offloading of instructions and writeback of the result(s).
CVA5
CVA5 is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide, Atomic, and Floating-Point extensions (RV32IMAFD). The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable. The CVA5 is derived from the Taiga Project from Simon Fraser University.
CVE4
CVE4 is a family of 32-bit, 4-stage in-order cores for embedded platforms that started from the PULP RI5CY core. Single configurations of these cores are maintained on different repositories and specialize in different embedded applications.
CVE2
CVE2 is a low-complexity, low-power, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements RV32[E|I][M]C instruction set architecture for achieving high-energy efficiency on control-oriented, computationally limited applications. Starting as a fork of the lowRISC Ibex core, the CVE2 is pared back to essential components and verified at industrial-grade.
CORE-V MCU
The CORE-V-MCU combines a 4 Stage CPU (currently CV32E40P (v1.0.0)). The CORE-V-MCU is a fully ready to go MCU with a great detail of documentation, it comes with various peripherals such as QSPI, UART, uDMA and many more, making up a fully working Microcontroller system. It comes with a detailed documentation and while it is made primarily for ASIC deployment it can run easily on an FPGA board, making it ideal for having a base system up and running in no time.
CORE-V-Verif
The CORE-V-VERIF project is a comprehensive, production-grade verification suite purpose-built for OpenHW Foundation’s portfolio of open source RISC-V cores. Core-V-Verif uses industry-standard SystemVerilog and UVM so commercial hardware engineers can easily run tests in simulators and provides ready-to-use testbenches, verification IP, and flows.
Unified Access Platform
The Unified Access Platform (UAP) provides a single, unified source of verified, open source RISC-V IP. It consolidates hardware and software components created as part of the TRISTAN consortium but has extended to Riogoletto HAL4SDV and many more European projects. The UAP provides clear visibility into technology maturity, usability, licensing, and integration workflow.
Programs
Program and project documentation for all OpenHW projects. Governance, specifications, and procedural guidelines.
Want to contribute?
OpenHW Foundation strives to be an open and welcoming ecosystem. We welcome contributions from individuals and organizations alike.
