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This repository was archived by the owner on Nov 17, 2023. It is now read-only.
CPUs perform best when tensors are allocated at a multiple of 64 bytes. The reason is that AVX512 instructions operate on 64 bytes at a time and memory access is more efficient when memory is aligned.
However, the above code pedantically only controls overall alignment of memory blocks, not the storage managers that divvy them up. Commit 3ef00b8 broke 64-byte alignment in the default storage manager.