Lastest Posts

PCI-SIG® is returning to Santa Clara, CA for our annual PCI-SIG Developers Conference (DevCon) on May 6-7, 2026 in the Santa Clara Convention Center.

The role of PCI Express® (PCIe®) architecture in modern embedded environments continues to expand due to its reliability, backwards compatibility and ability to facilitate high-bandwidth, low-latency data transfer between components.

As AI and cloud infrastructures scale, the demand for higher bandwidth, lower latency, and improved power efficiency continues to rise.

PCI-SIG® is proud to announce the PCI Express® (PCIe®) 8.0 specification, version 0.3 has received work group approval and is now available to members.

The PCI-SIG® Authorized Test Lab (ATL) Program was established in 2023 to provide members with another option to test their PCI Express® (PCIe®) t

Demands for a high bandwidth, low latency interconnect to address the needs of emerging applications like AI/ML, 800G Ethernet, Cloud and Quantum computing continue in the industry.

PCI Express® (PCIe®) technology is widely used in modern embedded and industrial environments due to its ability to facilitate high-bandwidth, low-latency data transfer between components.

At this year’s PCI-SIG® US Developers Conference 2025, held on June 11-12 in Santa Clara, California, the PCI-SIG Board of Directors recognized Sam Kocsis of Amphenol as the co-recipient of the 2025 Chairperson’s Award for his continued commitment as chair of the PCI-SIG Cabling Workgroup and con

At this year’s PCI-SIG® US Developers Conference 2025, held on June 11-12 in Santa Clara, California, the PCI-SIG Board of Directors recognized Nat Barbiero of AMD as the co-recipient of the 2025 Chairperson’s Award for his commitment as co-chair of the Protocol Workgroup PHY Logical Sub-team and

AI is accelerating at a pace few industries have ever witnessed. Every six months, model sizes are doubling, workloads are scaling across thousands of GPUs, and the demands on compute infrastructure are surging beyond anything imagined even a few years ago.

I am excited to share that PCI-SIG® has released the PCI Express® (PCIe®) 7.0 specification, version 0.9 for member review.

In today’s hyper-connected world of seamlessly integrated devices, systems and infrastructure, cybersecurity threats are becoming more sophisticated every day. It is important that the industry continue to improve security protection starting at the hardware level.

As we enter 2025, I am pleased to announce PCIe 7.0 specification, version 0.7 is now available for member review.

Every year, we take the opportunity to look back and reflect on all PCI-SIG® has accomplished as an organization and community in the advancement and promotion of PCI Express® (PCIe®) technology over the previous year.

PCIe technology is set to be leveraged as an important component in the AI infrastructure marketplace.

As Moore’s Law slows down and approaches its scalability limits due to semiconductor equipment limitations, the industry needs to seek new solutions to boost the performance and efficiency of CPUs.

The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global members that make PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global membership that makes PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

The storage landscape is rapidly evolving, led by advances in Artificial Intelligence (AI) and High-Performance Computing (HPC). These applications generate massive amounts of data that must be instantaneously processed, stored and analyzed in real time.

FMS: The Future of Memory and Storage is quickly approaching on Aug. 6-8, 2024, at the Santa Clara Convention Center, and has expanded its scope to encompass all tiers of Memory and Storage.

At this year’s PCI-SIG® US Developers Conference 2024, held on June 12-13 in Santa Clara, CA, the PCI-SIG Board of Directors recognized Gordon Getty of Teledyne LeCroy as the recipient of the 2024 Chairperson’s Award for h

The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global membership that makes PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global members that make PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

As the application space for PCI Express® (PCIe®) cabling has grown, PCI-SIG® has kept up the pace to meet industry needs for high-speed cabling solutions. In this blog, we answer some common questions about PCIe cabling and the recently released CopprLink™ cables.

Networking devices provide an essential role in facilitating communication between computers and internet networks.

Progress continues on the PCI Express® (PCIe®) 7.0 specification, which PCI-SIG® announced at US DevCon in June 2022.

There are many unique challenges in designing artificial intelligence (AI) and machine learning (ML) applications, and the exuberance around ChatGPT has highlighted the influence that AI can have on day-to-day life.

The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global membership that makes PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

As the complexity of computer workloads in the automotive market increase, so does the sophistication of computers in vehicles, along with the interconnect performance requirements. A unique emerging challenge is Automotive Functional Safety (FuSA).

We are happy to celebrate another successful year for PCI-SIG® and wanted to take a moment to reflect on the accomplishments our community has made this year in the advancement and implementation of PCI Express® (PCIe®) technology.

Author’s Note: This blog discusses new functionality introduced in the PCIe 6.0 specification, but please note that subsequent revisions have been published. Developers should always work from the latest revision to ensure they see all specification errata.

The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global membership that makes PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

Servers are challenged to process more intricate and diverse types of workloads in cloud, hybrid-cloud and enterprise data centers.

Author’s Note: This blog discusses new functionality introduced in the PCIe 6.0 specification, but please note that the PCIe 6.0.1 and PCIe 6.1 specification revisions have been published.

PCI-SIG® celebrated our 30-year milestone last year, and the “Meet the PCI-SIG Members” blog series is a way to highlight our diverse global membership that makes PCI-SIG what it is today.

Flash Memory Summit (FMS) 2023 is right around the corner on Aug. 8-10 at the Santa Clara Convention Center in Santa Clara, CA.

PCI-SIG® is pleased to share the PCI Express® (PCIe®) 7.0 specification, version 0.3 is now available to members. Version 0.3 of the specification indicates that the first review draft of the specification is complete and has received work group approval.

Today at our PCI-SIG® Developers Conference 2023 in Santa Clara, California we debuted a new report from ABI Research, “PCI Express Market Vertical Opportunity.” We are proud to o

A Conversation with Dean Gonzales, PCI-SIG® US DevCon 2023 Chairperson’s Award Recipient

A Conversation with Scott Knowlton, PCI-SIG® US DevCon 2023 Chairperson’s Award Recipient

PCI-SIG® is excited to invite members back to our annual PCI-SIG U.S. Developers Conference (DevCon) in the Santa Clara Convention Center in Santa Clara, CA from June 13-14.

PCI-SIG® is comprised of multiple technical work groups (TWGs) that develop PCI Express® (PCIe®) technology. Work groups are open to all PCI-SIG member company representatives and allow companies to shape current and future PCIe specifications.

The PCI-SIG® Members Forum is a resource for members to ask a variety of technical questions about PCI Express® (PCIe®) specifications and applications.

In 2022, PCI-SIG® introduced PCI Express® (PCIe®) 5.0 Compliance Testing to members. PCIe 5.0 specification official testing includes a maximum link speed of 32 GT/s.

The PCI-SIG® Developers Conference returned to Taipei, Taiwan for the first time since 2019 on Feb. 20-21 at the Taipei Marriott Hotel. With 674 total attendees, it was the highest-ever turnout for a DevCon.

PCI-SIG® is comprised of multiple technical work groups (TWGs) that work towards the development of PCI Express® (PCIe®) technology. Work groups are open to all PCI-SIG member company representatives and allow companies to further the PCIe specifications.

In early 2022, PCI-SIG® released the full version of the PCI Express® (PCIe®) 6.0 specification.

PCI-SIG® in 2022: A Year to Celebrate

By Mihaela Erler and Scott Knowlton, PCI-SIG MWG Co-Chairs

Advanced IP Design for PCI Express® Technology

By Scott Knowlton, PCI-SIG MWG Co-Chair

Around the World with PCI-SIG: Join Us at the 2022 International DevCons

By Richard Solomon, PCI-SIG Vice President and Developers Conference Chair

By Scott Knowlton and Mihaela Erler, PCI-SIG MWG Co-Chairs

The PCI-SIG® Board of Directors honored three individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology during the PCI-SIG US DevCon 2022 on June 21-22 in

During the PCI-SIG® US DevCon 2022, the PCI-SIG Board of Directors surprised two individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology.

By Al Yanes, PCI-SIG President and Board Chair

As PCI-SIG® celebrates its 30th year, the PCI-SIG Board of Directors recognized an individual for his countless hours of service and contributions to the development and expansion of the PCI Express (PCIe®) specification.

It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.

Following the release of the PCI Express® (PCIe®) 6.0 specification to members earlier this year, PCI-SIG® had the unique opportunity to participate in three IT industry podcasts.

With the ever-growing importance of security, we continue to see strong industry interest in Integrity and Data Encryption (IDE). As with any new technology, questions have been raised and addressed through new errata.

Introduction

For nearly three decades, PCI Express® (PCIe®) technology has served as the de facto high bandwidth, low latency interconnect. As the industry evolves to meet the needs of data-intensive applications, the PCIe specification has kept pace, enabling future innovation.

We are pleased to commence 2022 on a high note with the official release of the PCI Express® (PCIe®) 6.0 specification to members.

PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.

PCI-SIG® built upon our momentum from 2020 with another successful year in 2021. From progress on the PCIe 5.0 architecture compliance program to the impending release of the PCIe 6.0 specification, we have hit many exciting milestones.

I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.

The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations.

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

By: Hope Bovenzi, Strategic Marketing, Astera Labs

By Al Yanes, PCI-SIG® President and Board Chair

Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon

Manisha Nilange of Intel was honored at this year’s PCI-SIG US DevCon

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.

The PCI Express® (PCIe®) 6.0 specification will provide multiple features, including Transaction Layer Packet (TLP) payload, encoding and decoding, shared credit pooling, Forward Error Correction (FEC), CRC error correction, and more.

As part of our ongoing effort to broaden the adoption and deployment of PCI Express® (PCIe®) technology into diverse industry verticals, the PCI-SIG® Board of Directors recently announced the PCI-SIG Automotive Taskforce.

Is your company interested in speaking at PCI-SIG® Virtual Developers Conference 2021? The 

Many online resources cover the history and current state of industry development for the concept that, in Integrity and Data Encryption (IDE), we refer to as a Trusted Execution Environment (TEE).

With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.

Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG®.  We continued the momentum started in 2019 with PCIe® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engage with virtu

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

This year has been challenging for us all and we hope that you and your families are staying healthy and safe. Despite the trials that we have faced, PCI-SIG® is adapting our events and workshops to these new times and pressing on in specification development.

Given the shift to virtual events this year, PCI-SIG® has adapted to a primarily digital world via various online initiatives like educational webinars, blogs and more.

The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.

The upcoming PCI Express® (PCIe®) 6.0 specification will continue PCI-SIG’s® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.

Before the emergence of autonomous driving, our cars provided isolation from the outside world. We could move from point A to point B with the press of a pedal and a Mapquest print-out in the passenger seat.

Each year, over 800 PCI-SIG® member companies are invited to attend the PCI-SIG U.S. Developers Conference.

At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express® (PCIe®) specifications enable OCP systems today and how newer versions of PCIe w

We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.

The Internet of Things (IoT) Industry is rapidly growing in popularity and breadth of applications.

As I look back on 2019, I’m proud to report that it has been a banner year for PCI-SIG®.

According to Tractica, Artificial Intelligence (AI) and Machine Learning (ML) markets are set to grow to $118.6 billion by 2025—as  these new technologies are becoming the heart of our digital live

Our PCI-SIG® members have been hard at work. In 2017, we delivered PCI Express® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

From Israel to Europe and Japan to Taiwan, the PCI-SIG® Israel, Europe and APAC 2019 Developers Conference tour has come to an end for the year.

PCI-SIG® has enabled PCI Express® (PCIe®) technology to be cost-effective and easy to implement by supporting multiple form factors for a variety of applications.

The first installment of the PCI-SIG® educational webinar series, “Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential” premiered on October 9, 2019.

I’m pleased to share that PCI-SIG® continues to make great progress on the development of our next generation of PCIe® technology – the PCIe 6.0 s

PCI Express® (PCIe®) technology is deployed worldwide by PCI-SIG member companies, so it only makes sense that PCI-SIG® travels around the globe too.

Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 specification was first introduced almost 10 years ago.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express® (PCIe®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG® is excited to highlight our participation in the growth of flash storage.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express® and NVMe™ interfaces to the SD interface. The PCIe® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

Another PCI-SIG Developers Conference has come and gone, and we had a whopping 600+ member company attendees at this year’s event in Santa Clara.

I am happy to share that PCI-SIG® has begun developing the PCI Express® (PCIe®) 6.0 specification, targeted for release in 2021. The new specification is blazing the trail for interconnect technology as one of the first applications to reach 64GT/s transfer rates.

I am pleased to announce that PCI Express® 5.0 specification, Version 1.0— reaching 32GT/s transfer rates—has been released to our members in less than 2 years.

PCI-SIG® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

On January 22, 2019, the U.S. Cybersecurity and Infrastructure Security Agency issued an emergency directive to mitigate DNS infrastructure tampering intended to disrupt and redirect government and business communications.

This June 18-19, PCI-SIG and its 800+ member companies return to the Santa Clara Convention Center for the largest member event of the year: the Annual Members Meeting and Developers Conference.

PCI-SIG has built its reputation on delivering high quality PCI Express® (PCIe) specifications that have doubled bandwidth on average every three years, while maintaining full backwards compatibility with prior generations.

his year, I was lucky enough to be able to attend and present at the Open Compute Project Summit and though it has come and gone by now, I’m already looking forward to the next one! 

At PCI-SIG, we take pride in ensuring that our specifications operate without a hitch. However, sometimes PCI Express developers need to submit Engineering Change Requests (ECRs) to update parts of the specification so that PCIe integrated products can reach their optimal functionality.

This is already shaping up to be a busy year for PCI-SIG® with the pending release of the PCI Express® 5.0 specification targeted for the first qu

I’m happy to share that 2018 has been another productive year for PCI-SIG. In addition to significant progress in our specification development and compliance work, we also continued to provide educational resources to our members and the industry.

Our PCI-SIG® members have been hard at work. In 2017, we delivered PCI Express® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

The PCI-SIG Serial Enabling Workgroup (called the “SEG” for short) is the PCI-SIG workgroup charged with running the PCI Express® (PCIe®) compliance program.

By now, you probably know about the PCI-SIG Developers Conference which we hold in Santa Clara each year – a free event for our 750+ member companies with four tracks of presentations over two days.

PCI Express (PCIe®) has been widely adopted in a number of applications that range from small, power-constrained IoT sensors and mobile devices to servers and networking and communications equipment.

PCI Express® – also known as PCIe – used to get a bad rap for being power hungry on servers and PCs. But I’m happy to say that this is no longer the case. Are you aware that PCIe today is extremely power efficient with built-in low power features?

I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.

Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.

After successfully releasing PCIe® 4.0 Specification Version 1.0 last October, the members of the PCI-SIG® have been heads down and hard at work to ensure PCIe 5.0 specification is made a reality by 2019.

Press conference on June 5 to announce PCIe 5.0 spec updates

I recently attended the OCP Summit for the first time and I was impressed by the size of this growing event. The San Jose Convention Center was packed with industry experts – all eager to discuss how to move the Open Compute Project (OPC) forward.

I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website.