Feature challenge: add an aarch64 (host-native) backend so output runs and debugs natively on arm64 dev machines

[avrabe]

Filed by the PulseEngine challenge harness (synth v0.17.0). Feature challenge, not a defect.

Gap

synth emits Thumb-2 (Cortex-M) and RV32 bare-metal ELF only. On an aarch64 development host (Apple Silicon, arm64 Linux/CI), there is no way to execute or debug synth's output natively — every functional/debug check must go through QEMU/Renode emulation.

Why it matters for the toolchain's own testing

The differential-testing story (wasm in wasmtime as oracle vs synth's compiled artifact) and the DWARF/debugging story both get materially cheaper and faster if synth can target the host ISA:

• Native differential execution — run synth output directly, no emulator setup, no qemu semihosting shims; tighter loop, fewer moving parts in CI.
• Native source-level debugging — pair an aarch64 backend with the --debug-line DWARF work (Emit DWARF in the ARM/RISC-V ELF — synth drops debug info; bare-metal output is not source-debuggable #394) and you can lldb/gdb synth output on the same machine that built it, validating the line tables against real breakpoints instead of only llvm-dwarfdump --verify.
• A third backend is also a third oracle — divergence between the Thumb-2, RV32, and aarch64 lowerings of the same wasm is a cheap, powerful bug detector for the instruction selector.

Scope / suggestion

Even a minimal AArch64 (A64) integer-subset backend reachable via -b aarch64 (mirroring how -b riscv was added) would unlock native execution + debugging for the i32/i64/control-flow core that already has the strongest proofs. Float/SIMD can follow.

Acceptance idea

• synth compile add.wat -b aarch64 -o add.o produces a host-linkable object that runs and returns the same result as the wasm in wasmtime, and
• with --debug-line, a breakpoint on a known source line in lldb stops at the matching instruction.

Happy to contribute the differential + debug acceptance probes from the challenge harness.