feat(vcr-sel): cmp→select → IT-block predication fusion, flag-off (VCR-SEL-004, #242, #428)

[avrabe]

What

Adds the late peephole fuse_cmp_select (VCR-SEL-004, epic #242) — the cmp→select half of gale's #1 hot-path size/cycle lever (#428).

The selector lowers a select whose condition is a comparison to a materialize-then-re-test sequence:

cmp a,b ; SetCond D,c ; cmp D,#0 ; movne dst,v1 ; moveq dst,v2

The SetCond and the select's cmp D,#0 are pure overhead — the comparison already set NZCV, and each SelectMove is an independent flag-preserving IT;MOV. The peephole collapses the pair onto the comparison's own flags (delete SetCond + cmp D,#0, retarget the moves to c / invert(c)), yielding the textbook predicated clamp:

cmp a,b ; movc dst,v1 ; mov{!c} dst,v2     (−2 instructions / fused select)

Real-fixture objdump (control_step), flag-on:

flag-off: cmp r0,#19 ; movcc.w r8,#1 ; movcs.w r8,#0 ; cmp.w r8,#0 ; movne r5,r6   (5 insns)
flag-on:  cmp r0,#19 ; movcc r5,r6                                                  (2 insns)

Scope — select half only

The artifact title is "select/br_if". This PR lands the select→movCC half. The br_if→predicated-branch half is not done (branch consumers are unmodeled by reg_effect and never match) — deferred follow-up. Artifact note scoped accordingly.

Sound by construction (each guard has a negative unit test)

• flags reused only when nothing clobbers them in the SetCond→cmp window (clobbers_flags — tight ldr/str/push/pop/nop allowlist);
• the boolean deleted only when provably dead — a downstream redefinition before any read / unmodeled op / branch / end (reg_dead_by_redef, so an R0 return value is never mistaken for dead);
• [i-1] must be the flag-setting compare; dst != D.

Plus Condition::invert() (exhaustive over all 10 conditions).

Frozen-safe / gated

Wired into arm_backend.rs after range-realloc (final register identities for the dead-D proof) and before encode, behind SYNTH_CMP_SELECT_FUSE=1. Default-off ⇒ a literal no-op ⇒ the three frozen differentials (control_step 0x00210A55 / flat+inlined flight_algo 0x07FDF307 / divseam) stay bit-identical, un-rerun.

Validation (this step)

• 8 liveness unit tests — positive incl. the gust_mix ×2 in-place clamp; 5 negative guards (D live, flag-clobber in window, predecessor not a compare, dst aliases D, no redef);
• 3 encoder byte-tests — all 10 IT <cond>; MOV conditions, exact bytes for the LT/GE + LO/HS pairs fusion newly produces;
• rewrite-count > 0 on real fixtures (control_step 3, flight_algo/controller 5–6, filter_axis 0 — correctly nothing to fuse);
• arm-none-eabi-objdump diff confirms the predicated clamp replaces the 5-insn materialize+re-test, and unsafe sites (boolean reused) correctly decline.

Deliberately deferred (owed by the default-on flip step — NOT done here)

• Execution-level differential under the flag (VCR-ORACLE-001 Rust unicorn harness, task Create documentation structure #6) + gale's gust_codegen_bench on G474RE (≤1.3× fn-only) — the agreed on-silicon kill-criterion. Only then does the flag flip default-on and the tag cut.
• Empirical gap that differential must close: every fused site on the real fixtures was the in-place single-move form, so the two-move moveq→mov{invert(c)} path (where invert() matters at runtime) has run in unit/encoder tests but never selector→fusion→encoder→exec on a real function. The flip's differential must include a fixture forcing a non-in-place select (e.g. val2 a live param). (wasm-synth z_impl: sem->count not incremented on give (stays 0, limit=1) on hardware — u64-packed new_count miscompiled; binary sem never signals (v0.11.12) #204/arm32 encoder drops the register index on indexed loads/stores ([r11] instead of [r11, rN]) #206 IR-right/composition-wrong lesson.)
• br_if→predicated-branch half (separate follow-up).

Refs #242, #428. Baseline v0.12.0.

🤖 Generated with Claude Code

[codecov]

Codecov Report

❌ Patch coverage is 94.38202% with 15 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-synthesis/src/liveness.rs	95.95%	10 Missing ⚠️
crates/synth-backend/src/arm_backend.rs	28.57%	5 Missing ⚠️

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