verify(vcr): VCR-VER-001 program gate DEMONSTRATED — patch-accretion reverses (#242) - #659
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…reverses (#242) The North-Star program's falsification test, attempted and measured (evidence: scripts/repro/vcr_ver_001_gate.md): 1. The v0.11.20 reciprocal-mult cost-gate — load-bearing when added (v0.11.19 hard-failed control_step's 4x const div_u) — was DELETED outright in PR #322 once the #320 spill retry covered its case: full differential bit-identical, cycles trivially equal, no new cost-gate since. The roadmap's pass-criteria met literally; the artifact goes proposed -> implemented. 2. The #496 register-exhaustion hard-decline is REVERTABLE behind SYNTH_SPILL_ON_EXHAUST (#580, default off = fix stays): - red case green: r12_spill_496 differential PASS flag-on (incl. the 0x00210A55 / 0x07FDF307 silicon anchors); all five pressure differentials PASS on the reversal bytes - frozen pinned goldens 10/10 in BOTH flag states; the three result anchors' default-path bytes are byte-identical flag-on (new lock: vcr_ver_001_gate_242.rs); declines 14 -> 8 across the corpus - HONEST HOLD: weighted cycle proxy regresses on i32 shapes (+30.4% spill_on_exhaust_242, +32.4% spill_rung_581, +8.0% high_pressure_i32, +120% signed_div_const 34->76 B; i64 shapes improve -5.5%/-1.4%) — the decline remains load-bearing FOR CYCLES, not correctness. Missing capability named: post-exhaustion code quality on the optimized path (allocation-time spill placement/coalescing). The default-on flip stays a separate later PR (#580 silicon hold). Flag-off this change is docs + roadmap + one additive test: no codegen bytes move; frozen gate green; goldens NOT re-pinned. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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…nst-div guards (#242, the PR #659 verdict) (#672) PR #659 held the SYNTH_SPILL_ON_EXHAUST flip on a measured i32-shape cycle regression and named the missing capability: post-exhaustion code quality on the optimized path. Root cause of the unreached allocation-time Belady slots: - fresh-monotonic slots defeat the overwrite-only frame-slot DCE (#515); - the eviction store's source is redefined immediately, defeating forward_stack_reloads; - spill_rechoice's rename deadness proof is segment-local — R2/R3 are never touched again on bridge streams, so "possibly live-out" declined them, and exact SegmentTrace equality rejected any fresh-register rename; - signed_div_const additionally paid for const-divisor trap guards the direct selector elides (#209 Opt 1a). Extensions, ALL scoped to functions the #580 machinery actually shaped (OptimizerBridge::spill_on_exhaust_fired — flag-on leaves every untouched function byte-identical, locked by vcr_ver_001_gate_242 + frozen 10/10 run in both flag states; flag-off is bit-for-bit the shipping pipeline): - scratch_dead_at: function-level R2/R3 exit-deadness (conservative at any branch/call/unmodeled op) feeding rename_kill_def; trace equality modulo provably-dead exit entries; per-pair pressure commit; byte-shrinking count-neutral folds admitted; - constant rematerialization of spilled single-instruction consts in spill_forward_segment (movt RMW kills the shape — the #582 discipline); - bounded fixpoint of the cleanup triple + late elide_dead_frame; - terminal-segment relaxed live-out pinning in range-realloc (only R0/R1 observable past bx lr pre-prologue; VCR-RA-003 validator run with the same exemptions; reload-free segments only); - const-divisor trap-guard elision in DivS/DivU/RemS/RemU (single-def Const scan, total-or-disabled def enumeration; c=0 keeps all, DivS c=-1 keeps the overflow guard). Cycle proxy (scripts/repro/postex_cycle_proxy.py, wasmtime-matched): spill_on_exhaust_242 +30.4%→+17.4%, spill_rung_581 +32.4%→+8.8%, high_pressure_i32 +8.0%→−24.0%, signed_div_const +120%→−33.3%, i64 pair/pool −16.4%/−2.9%. Two fixtures still miss ≤+5%: the residual is alloc_i32_scratch's fixed R4-R8 dest pool vs the direct selector's nine registers — the Track-A allocator replacement itself (see the gate doc's "residual, named" section; a reload-pool widening was tried and reverted, measured strictly worse). The flip stays HELD (#580). Gates: cargo test --workspace green; frozen anchors 10/10 + gate lock in BOTH flag states; r12_spill_496 / spill_on_exhaust_242 / i64_pair_exhaust_587 / i64_spill_pool_587 / spill_rung_581 differentials PASS flag-on; fmt + clippy -D warnings clean. Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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The gate
VCR-VER-001is the North-Star program's falsification test: a previously load-bearing greedy fix becomes revertable — patch-accretion reverses. Roadmap pass-criteria: at least one previously load-bearing greedy-fix removed with the full differential bit-identical and cycles equal-or-better; no new cost-gate introduced.This PR attempts the gate, measures everything, and flips the artifact
proposed → implemented. Full evidence note:scripts/repro/vcr_ver_001_gate.md.Candidate survey
SYNTH_SPILL_ON_EXHAUST(#580) — correctness criteria all hold; the cycles criterion measurably FAILS on i32 shapes → flip stays held, missing capability named// #NNNguards inoptimizer_bridge.rsThe #496 reversal vs the three criteria (measured at f8c6826)
(a) original red case stays green flag-on —
r12_spill_496_differential.pyPASS (both original silicon victims, incl.control_step = 0x00210A55,flight_algo = 0x07FDF307);spill_on_exhaust_242,i64_pair_exhaust_587,i64_spill_pool_587,spill_rung_581differentials all PASS on the reversal bytes;signed_div_const+high_pressure_i32flag-on bytes execution-verified vs wasmtime.(b) differential suite bit-identical or better — frozen pinned goldens 10/10 in both flag states; the three result anchors' default-path bytes byte-identical flag-on (new lock
vcr_ver_001_gate_242.rs); declines 14 → 8 across the corpus. Per-function bytes/cycles table in the evidence note. Honest numbers: the weighted cycle proxy (insns + mem accesses, unicorn, wasmtime-matched) regresses on i32 shapes —spill_on_exhaust_242+30.4 %,spill_rung_581+32.4 %,high_pressure_i32+8.0 %,signed_div_const+120 % (its 34-B direct lowering becomes a 76-B optimized-path compile) — while the i64-pair shapes improve (−5.5 %, −1.4 %).(c) frozen anchors — byte-identical flag OFF (10/10, zero codegen change in this PR); flag ON changes bytes only on unpinned pressure fixtures; the refreeze-ritual differentials were re-run on those new bytes (all PASS) and the goldens were not re-pinned — the flip is a separate later PR.
The honest verdict
The gate passes on the cost-gate deletion (the literal pass-criteria). The deeper #496 reversal is correctness-complete but performance-regressive on i32 shapes: the decline remains load-bearing for cycles, not correctness. Missing capability (VCR-RA follow-on): post-exhaustion code quality on the optimized path — allocation-time Belady spill emits more stack traffic than the direct selector's operand-stack spill (16→22 accesses/call on
spill_on_exhaust_242), and frame-slot-DCE/stack-fwd don't reach allocation-time slots. TheSYNTH_SPILL_ON_EXHAUSTdefault-on flip stays held (#580) on closing that gap + gale G474RE cycles.Changes (flag-off: zero bytes move)
artifacts/verified-codegen-roadmap.yaml— VCR-VER-001proposed → implemented+ evidencescripts/repro/vcr_ver_001_gate.md— the full evidence note (tables + reproduce commands)crates/synth-cli/tests/vcr_ver_001_gate_242.rs— NEW lock: the reversal flag must leave the three frozen result anchors' default-path bytes untouchedGates run
frozen anchors 10/10 ·
cargo test --workspacegreen (108 suites, 0 failures) · fmt + clippy-D warningsclean ·rivet validate0 non-xref errors +rivet coverageexit 0 (pinned v0.23.0, same as CI)🤖 Generated with Claude Code