feat(#798): RV32 active data segments SHIP — .wasm_data records + linker placement + startup copy, read-back hard gate

[avrabe]

Closes #798. v0.48 Wave-1 Lane 3.

What

The RV32 single-base scheme (s11 = __linear_memory_base, zeroed RAM) shipped a .text-only object: active data segments were silently dropped — every nonzero initializer byte read 0x00 at runtime (found by the VCR-VER-003 phase-2 probe #777; v0.47/#797 held a loud warning). This PR ships them — the real fix, not the decline:

• Object: segments pack into sparse per-segment records [u32 off][u32 len][bytes][pad4] (declaration order; synth_core::static_data_addr::pack_segment_records) emitted as a .wasm_data PROGBITS (SHF_ALLOC) section. A far segment costs 8 + len flash bytes — no dense image. Data-free modules ship no section and are whole-object byte-identical (unit-gated).
• Linker script (synth riscv-runtime): flash-resident .wasm_data output section with __wasm_data_records_start/end, placed before _data_load is pinned. An old script + new startup fails the link loudly (undefined symbol) instead of dropping data again.
• Startup: the reset path walks the records and byte-copies each to __linear_memory_base + off before main — record order = declaration order, so WASM later-wins overlap semantics hold structurally (the 0.43.0: #746 fix relocates but MISCOMPILES the wide-static copy path — silent wrong bytes (was: skip) #757 lesson).
• VCR-VER-003 arm (hard gate): the emit path reads the emitted blob back (served_image_from_records — never a recompute, mirror-pinning structurally excluded) and validate_served_image hard-errors the compile on any served/runtime disagreement. A segment past the declared memory is refused (instantiation would trap, default --cortex-m self-contained image silently DROPS active (data) segments: .linear_memory is NoBits, initializer bytes absent -> every load from an initialized region reads 0 (silent miscompile) #758 parity). The v0.47 warning is gone; the library Backend::compile_module path ships + validates too.

Red → green

• De-vacuated control_step_riscv_differential.py: the old harness copied wasmtime's instantiated memory into unicorn, masking the drop (a vacuous gate). It now initializes linmem only from the shipped .wasm_data records. On the pre-fix binary (ac79fb3): loud FAIL, and the semantic red is proven — zeroed-linmem execution returns 0x00000000 for (3000,50,40,0) where wasmtime returns 0x00210a55. Post-fix: 5/5 vectors match incl. gale's reference 0x00210a55.
• New full-boot oracle scripts/repro/rv32_data_798_boot_differential.py: synth compile → riscv-runtime → clang(riscv32) + ld.lld → unicorn boots fw.elf from _reset — the REAL generated startup copy loop initializes linmem; overlapping segments serve the later-wins image (aabb1122) and get() equals wasmtime (0x2211bbaa). PASS locally.
• Red-first unit gates: a reversed (first-wins) record pack fails validate_served_image at the classic 0.43.0: #746 fix relocates but MISCOMPILES the wide-static copy path — silent wrong bytes (was: skip) #757 byte; declaration order passes. Malformed blobs parse to None (loud).

Refreeze ritual

All 12 *_riscv_differential.py scripts re-run PASS on the new bytes. Frozen RV32 .text is unchanged (control_step .text sha identical pre/post; data-free objects byte-identical) — frozen_fixtures_rv32_text_is_bit_identical_oracle_001 green with no re-pin needed; the compile-success freeze that held the v0.47 warning is moot because the compile stays green by shipping, and its differential now actually reads the segment (de-vacuated per #797's finding).

Gates

• cargo test --workspace green (126 suites), cargo fmt --check, clippy -D warnings clean
• scripts/claim_check.py: 21/21 — claims/roadmap updated to the shipped state + new count-eq pin holding the RV32 served image to the emitted blob read-back
• e2e tests: records-verbatim, both-records-in-order (overlap), no-section (data-free), instantiation-trap refusal

🤖 Generated with Claude Code

https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L

[codecov]

Codecov Report

❌ Patch coverage is 88.03419% with 42 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-backend-riscv/src/backend.rs	0.00%	28 Missing ⚠️
crates/synth-cli/src/main.rs	62.96%	10 Missing ⚠️
crates/synth-backend-riscv/src/elf_builder.rs	98.41%	2 Missing ⚠️
crates/synth-core/src/static_data_addr.rs	98.24%	2 Missing ⚠️

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