Log message:
cad/py-PyRTL: Update to 1.0.2

Changelog:
## [1.0.2] - 2026-07-22

### Fixed

- Fixed a  `CompiledSimulation` `arm64` bug introduced in `1.0.1`. Added an \ 
`arm64` GitHub workflow to catch such regressions in the future.

## [1.0.1] - 2026-07-22

### Changed

- Significant `Simulation` performance speedups (tested with \ 
[`pyrtlnet`](https://github.com/UCSBarchlab/pyrtlnet)):
  class | method | speedup
  ---: | :--- | ---:
  `Simulation` | `step()` | 40%
  `FastSimulation` | `__init__()` | 10%
  `FastSimulation` | `step()` | 15%
  `CompiledSimulation` | `__init__()` | 65%
  `CompiledSimulation` | `step()` | 30%
- Documentation improvements.

### Fixed

- Fixed a `CompiledSimulation` bug when the first arg to `concat` crosses a \ 
64-bit boundary in the `concat`'s output.

Log message:
cad/py-PyRTL: Update to 1.0.0

Changelog:
1.0.0:
Added

  * PyRTL Floating point library (@gaborszita)
  * Registers can be constructed with a State IntEnum to simplify construction
    of state machines.

Changed

  * Improved CompiledSimulation's performance.
  * output_to_verilog now supports custom module_names. (@devmam999)
  * Minor improvements to wire_struct and wire_matrix.
  * Minor improvements to WaveDrom output.
  * Many documentation improvements.

Fixed

  * Fix WaveDrom trace output in Jupyter Notebooks. (@ryoon
  * render_trace raises PyrtlError when called with an empty SimulationTrace. (
    @gaborszita)

Log message:
cad/py-PyRTL: Fix the error from render_trace() on Jupyter

* Do not fail with 'Javascript Error: $ is not defined'.
* Bump PKGREVISION.

Log message:
cad/py-PyRTL: Update to 0.12

Changelog:
0.12 - 2025-07-28
Added

    GateGraph is an alternative PyRTL logic representation, designed to simplify \ 
analysis.

Changed

    Rewrote output_to_verilog and output_verilog_testbench. The new \ 
implementation's output should be much easier to read:
        Single-use expressions are inlined.
        Try mangling unusable WireVector and MemBlock names first, before \ 
assigning them entirely new names.
        Add comments to the generated Verilog that show the un-mangled names.
    Many documentation improvements:
        Most methods and functions now have examples.
        Consistently use canonical top-level pyrtl.* names, rather than \ 
module-level names (pyrtl.WireVector, not pyrtl.wire.WireVector).
        Enabled intersphinx for clickable standard library references (list, \ 
dict, etc).
        Set up doctest for examples, to verify that documentation examples still \ 
work.
    Switched from pylint and pycodestyle to ruff:
        Applied many ruff fixes.
        Reformatted the code with ruff format.
        Updated tox to run ruff check and ruff format.

Removed

    Removed remaining Python 2 support.

Fixed

    Fixed XOR implementation in and_inverter_synth pass (@EdwinChang24)
    output_verilog_testbench should not re-initialize RomBlocks.
    FastSimulation was not setting init_memvalue correctly (renamed to \ 
SimulationTrace.memory_value_map).
    Specify bitwidths for Verilog initial register and memory values. They were \ 
previously unsized constants, which are implicitly 32-bit signed, which could \ 
cause surprises.

Log message:
cad/py-PyRTL: Update to 0.11.3

Changelog:
## [0.11.3] - 2025-06-12

### Added

- An optimization pass to [optimize inverter \ 
chains](https://github.com/UCSBarchlab/PyRTL/blob/d5f8dbe53f54e61e1d54722449e4894b885243c7/pyrtl/passes.py#L130)
- `one_hot_to_binary` encoder \ 
([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.helperfuncs.one_hot_to_binary))
- `binary_to_one_hot` decoder \ 
([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.helperfuncs.binary_to_one_hot))

### Changed

- More support for signed integers: Signed integers can now be used in `RomBlock`'s
  `romdata`, `Simulation`'s `mem_value_map`, and Verilog-style register reset values.
- Improved documentation:
  - \ 
[conditional_assignment](https://pyrtl.readthedocs.io/en/latest/basic.html#module-pyrtl.conditional)
  - [WireVector \ 
equality](https://pyrtl.readthedocs.io/en/latest/basic.html#wirevector-equality)

### Fixed

- Use iteration instead of recursion to avoid stack overflow in `find_producer`.

Log message:
py-PyRTL: remove unused test dependencies

Log message:
py-PyRTL: add missing tool dependency

Fix testing and add test status.

Log message:
cad/py-PyRTL: Update to 0.11.2

Changelog:
### Added

- Added an `initialize_registers` option to `output_to_verilog`
  documentation

### Changed

- Improved handling of signed integers.

### Fixed

- Fixed a `wire_matrix` bug involving single-element matrices of `Inputs` or \ 
`Registers`.