PASCAL Research Group: Home

Programming LAnguages
and StatiC AnaLysis Group

The PASCAL Research Group is affiliated with the Institute of Computer Software and the School of Computer Science at Nanjing University. Our research focuses on static program analysis, aiming to develop effective techniques and practical tools for addressing challenging problems in both software and hardware systems.

We have developed several platforms that have attracted attention from the research and developer communities:

Tai-e

Java & Android

Tai-e is a general-purpose static analysis framework for Java and Android.

Qihe

Verilog

Qihe is a general-purpose static analysis framework for Verilog.

Vide

SystemVerilog

Vide is a modern coding IDE for SystemVerilog.

News

March 20, 2025
Pinned 📢我们现在开放【实习申请】【研究生申请】，欢迎有志于探索程序分析的同学加入我们的团队！✨
October 27, 2026
Our paper “When Absence Speaks: A Null-Aware Approach for Taint Analysis” has been accepted by ICSE’27. Congratulations to Zhiwei, Menglong, Yufei, Hengbin, and Yinning! This work presents a simple yet effective approach for recovering missing taint flows, improving the vulnerability detection capability of general-purpose Java taint analysis.
August 12, 2026
Our paper “When FPGA Meets Dataflow Analysis: An Explorative Step” has been accepted by OOPSLA’26. Congratulations to Fang Wei, Qinlin, Nairen, and Jiacai! This is the first work that explores designing specialized hardware to accelerate static analysis.
August 12, 2026
Our paper “Heap Abstraction via Early-Confluent Object Merging for Pointer Analysis” has been accepted by OOPSLA’26. Congratulations to Jinpeng, Yufei, and Zhongsheng! This work presents a heap abstraction that improves pointer analysis efficiency while preserving precision in a client-independent manner.
May 30, 2026
We are excited to announce VIDE, an open-source modern coding IDE for Verilog / SystemVerilog, bringing more than a dozen coding facilities that traditional hardware IDEs often lack. Led primarily by Jiayan Wu and Jiarong Hong, the project took three years to build and now totals ~60K lines of code. Learn more at vide.pascal-lab.net.
April 04, 2026
We’re pleased to announce that our paper describing Qihe, the static-analysis framework for Verilog that we previously released, has been accepted to PLDI’26. The paper is titled “Exploiting Sophisticated Static Analysis for Verilog”. Congratulations to Qinlin, Nairen, Jinpeng, and Jiacai! Watch Qihe’s introductory video and try it from the project homepage.
January 17, 2026
We are pleased to announce the release of Qihe, the first general-purpose static analysis framework for Verilog. For further resources, please visit the Qihe project homepage or watch the introductory video.
November 18, 2025
Our paper “ChiSA: Static Analysis for Lightweight Chisel Verification” has been accepted by POPL’26. Congratulations to Jiacai, Qinlin and Zhongsheng! This is the first static analysis framework for Chisel.