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stm32gx improvements - #910
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Nightwalker-87 merged 6 commits intoApr 6, 2020
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add a 'has_dual_bank' info to flash param, helping handling a couple of cases - selecting over dual bank specific code path without handling multiple chip id all over the code. - handling dual bank mode dynamic configuration
g4 cat3 devices can be configured in two mode via option bytes: - dual bank, 2x256kib, 2KiB pages. - single bank, 1x512KiB, 4KiB pages. in anycase, these have two banks, and need to be handled with more care. -> read optr after loading flash params to patch page size. -> in single bank mode, mass erase _must_ be triggered by applying MER1 and MER2 bits. erasing half of the flash will lead to a pgserr.
toggle proper MER bits, taking in account dual bank mode enabled or not.
only implement it for g0/g4 for now, but this is most probably a must for all chips.
Nightwalker-87
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Merci 🥇 |
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Hi,
here are a few patches to improve g4/g0 support
has_dual bank flag could probably avoid multiple device type check around the code with a bit of work.
flash programming check could probably be added in page erase and flash write and extended to other devices, to debug some silent issues.