[TRTLLM-12342][feat] Ring Attention, Unified Context Parallel for VisualGen#13821
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📝 WalkthroughWalkthroughThis PR introduces ring-based sequence parallelism via a new ChangesRing Attention & Sequence Parallelism Infrastructure
Model Integration & Refactoring
CLI & User-Facing Interface
Tests
Sequence DiagramsequenceDiagram
participant User as User / CLI
participant Config as Config & Mapping
participant Attn as Attention Module
participant Ring as RingAttention
participant Backend as Inner Backend
participant Sharder as SequenceSharder
participant Model as Visual Gen Model
User->>Config: Provide ring_size, ulysses_size
Config->>Config: VisualGenMapping: fixed dim order, seq properties
Config->>Attn: Pass config with ring_size, ulysses_size
Attn->>Ring: Wrap backend if ring_size > 1
Attn->>Attn: Wrap with UlyssesAttention if ulysses_size > 1
Model->>Sharder: Create SequenceSharder from mapping
Model->>Sharder: shard(hidden_states, img_ids, txt_ids)
Sharder->>Sharder: Distribute sequence chunks to ranks
Model->>Backend: Process local sequence chunk
Ring->>Ring: P2P exchanges with neighbors (if ring_size > 1)
Ring->>Backend: forward_with_lse per chunk
Ring->>Ring: Online softmax/LSE merge
Model->>Sharder: gather(hidden_states)
Sharder->>Sharder: All-gather sequence dimension
Sharder->>Model: Reconstruct full sequence
Estimated code review effort🎯 4 (Complex) | ⏱️ ~75 minutes The PR introduces substantial new infrastructure ( Suggested labels
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Actionable comments posted: 8
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⚠️ Outside diff range comments (7)
tensorrt_llm/_torch/visual_gen/config.py (1)
61-104:⚠️ Potential issue | 🟡 Minor | ⚡ Quick winDocumentation inconsistency: class docstring says
dit_ring_sizeis not supported, but field comment says "Supported".The class docstring at lines 70-71 lists
dit_ring_sizeunder "Not Yet Supported", but the field comment at line 104 now says "# Supported". Please update the class docstring to reflect the current support status.Proposed fix for class docstring
Currently Supported: - dit_cfg_size: CFG (Classifier-Free Guidance) parallelism - dit_ulysses_size: Ulysses head-sharding parallelism - dit_attn2d_row_size, dit_attn2d_col_size: Attention2D context parallelism + - dit_ring_size: Ring attention context parallelism Not Yet Supported: - dit_tp_size: Tensor parallelism (not implemented) - - dit_ring_size: Ring attention context parallelism (not implemented) - dit_dp_size, dit_fsdp_size: Other parallelism types🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/visual_gen/config.py` around lines 61 - 104, The class docstring for ParallelConfig is inconsistent about dit_ring_size: update the docstring to mark dit_ring_size as supported (moving it out of the "Not Yet Supported" list or changing its line to "Supported") so it matches the field comment and current behavior; locate the ParallelConfig class docstring and change the bullet mentioning dit_ring_size (previously under "Not Yet Supported") to reflect that dit_ring_size is supported alongside dit_ulysses_size, or adjust wording to indicate supported vs not supported features consistently with the dit_ring_size field.tensorrt_llm/_torch/visual_gen/attention_backend/interface.py (1)
1-1:⚠️ Potential issue | 🟡 Minor | ⚡ Quick winUpdate copyright year to include 2026.
Per coding guidelines, the copyright header should be updated to reflect the year of latest modification.
Proposed fix
-# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/visual_gen/attention_backend/interface.py` at line 1, Update the copyright header in the file by changing the year portion from "2025" to include 2026 (e.g., "2025-2026" or "2026" per project convention) so the SPDX header reflects the latest modification year; edit the top-line text that currently reads "Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES" to the updated year string.tensorrt_llm/_torch/visual_gen/modules/attention.py (1)
1-6:⚠️ Potential issue | 🟡 Minor | ⚡ Quick winMissing NVIDIA copyright header.
Per coding guidelines, all Python source files should contain an NVIDIA copyright header with the year of latest modification and Apache 2.0 license notice.
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/visual_gen/modules/attention.py` around lines 1 - 6, Add the required NVIDIA copyright header and Apache-2.0 license notice at the top of the tensorrt_llm/_torch/visual_gen/modules/attention.py file (above the existing imports); include the latest modification year, the NVIDIA copyright holder line, and the full Apache License, Version 2.0 boilerplate or SPDX identifier so the file complies with the project's licensing header convention.tensorrt_llm/_torch/visual_gen/models/wan/transformer_wan.py (1)
1-9:⚠️ Potential issue | 🟡 Minor | ⚡ Quick winMissing NVIDIA copyright header.
Per coding guidelines, all Python source files should contain an NVIDIA copyright header with the year of latest modification and Apache 2.0 license notice.
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/visual_gen/models/wan/transformer_wan.py` around lines 1 - 9, This file missing the required NVIDIA copyright header; add the standard NVIDIA copyright and Apache-2.0 license header comment block at the very top of tensorrt_llm/_torch/visual_gen/models/wan/transformer_wan.py (above the existing imports), with the correct year of latest modification and header text that matches our repo template so it appears before the first symbol (imports like math, torch, etc.) and ensures license metadata is present.tensorrt_llm/_torch/visual_gen/attention_backend/flash_attn4.py (1)
171-186:⚠️ Potential issue | 🟡 Minor | ⚡ Quick winIncorrect method name:
supports_lseshould besupport_lse.The base class
AttentionBackenddefinessupport_lse(), which is called throughout the codebase (e.g.,parallel.py:303,parallel.py:463). The newly added method at line 185 is namedsupports_lse()(with an extra 's'), which does not match the interface and will not be called by code expectingsupport_lse().Rename the method to
support_lse()to match the base class and maintain consistency with the rest of the codebase.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/visual_gen/attention_backend/flash_attn4.py` around lines 171 - 186, The class defines support_lse(self) at the top but later adds a misnamed supports_lse(cls) duplicate; remove or rename the incorrect supports_lse method to support_lse (and avoid duplicate definitions) so the class only implements the expected classmethod support_lse() used by the codebase (refer to the methods support_lse and supports_lse in flash_attn4.py and ensure the class uses support_lse matching AttentionBackend's interface).tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py (1)
1-4:⚠️ Potential issue | 🟠 Major | ⚡ Quick winAdd the standard SPDX header to this modified test file.
This file is touched by the PR, but it still lacks the repository-mandated NVIDIA copyright / Apache-2.0 header.
As per coding guidelines,
**/*.{cpp,h,cu,cuh,py}:All source files (.cpp, .h, .cu, .py) should contain an NVIDIA copyright header with the year of latest modification and Apache 2.0 license notice.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py` around lines 1 - 4, Add the standard NVIDIA SPDX header and Apache-2.0 notice to the top of the modified test file tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py: prepend the repository-mandated copyright/license block (including the year of latest modification and SPDX-License-Identifier: Apache-2.0) as used across other source files, ensuring it appears before the module docstring and imports so the file now contains the required header for VisualGenMapping tests.tensorrt_llm/_torch/visual_gen/mapping.py (1)
1-9:⚠️ Potential issue | 🟠 Major | ⚡ Quick winAdd the standard SPDX header to this modified source file.
This file now has new production code but still starts without the repository-required NVIDIA copyright / Apache-2.0 header.
As per coding guidelines,
**/*.{cpp,h,cu,cuh,py}:All source files (.cpp, .h, .cu, .py) should contain an NVIDIA copyright header with the year of latest modification and Apache 2.0 license notice.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/visual_gen/mapping.py` around lines 1 - 9, This file is missing the repository-required NVIDIA SPDX/Apache-2.0 header; add the standard SPDX header and copyright/license block at the top of tensorrt_llm/_torch/visual_gen/mapping.py so all new production sources comply with the policy, keeping the rest of the module (including VisualGenMapping, DeviceMeshTopologyImpl, build_mesh and the shared DeviceMeshTopologyImpl.device_mesh) unchanged.
🧹 Nitpick comments (1)
tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py (1)
105-107: ⚡ Quick winPlease exercise the new flattened sequence mesh directly.
SequenceShardernow consumesseq_rank,seq_group, andring_group, but this suite only asserts the private_dim_namestuple and the older per-dim groups. A small 4-GPU check thatseq_rankfollows the cp-major / ulysses-minor linearization and that a collective overseq_groupspanscp_size * ulysses_sizewould cover the API this PR actually introduced.As per coding guidelines,
Coverage expectations: Assess whether new/changed tests cover happy path, important edge cases, and failure modes relevant to the feature or fix.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py` around lines 105 - 107, Add a test that exercises the new flattened sequence mesh instead of only asserting _dim_names: instantiate VisualGenMapping/SequenceSharder for a 4-GPU configuration (use world_size=4) and verify that seq_rank is assigned following cp-major / ulysses-minor linearization (i.e., seq_rank changes fastest across ulysses then cp), that seq_group and ring_group are populated per the new API (seq_rank, seq_group, ring_group fields on SequenceSharder), and assert that a collective over seq_group spans cp_size * ulysses_size (use the SequenceSharder.cp_size and .ulysses_size to compute expected group size). Ensure the test checks the happy path mapping for all ranks (iterate ranks 0..world_size-1) rather than only checking private _dim_names.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Inline comments:
In `@examples/visual_gen/visual_gen_wan_t2v.py`:
- Around line 309-320: The CI failures are caused by trailing whitespace and
formatting in the block that checks args.ulysses_size and sets
num_heads/logger.info/parallel_str; remove any trailing spaces (especially after
the closing parenthesis on the logger.info line) and reflow the f-strings to
satisfy ruff formatting (keep the f-strings split sensibly or join into one
line) so that the code around args.ulysses_size, num_heads, logger.info, and
parallel_str has no trailing whitespace and conforms to the project's
line-length/format rules.
In `@tensorrt_llm/_torch/visual_gen/attention_backend/parallel.py`:
- Around line 559-584: The current gate uses k.shape[1] != q.shape[1] and only
rejects PredefinedAttentionMask.CAUSAL, which lets equal-length cross-attention
and non-FULL masks erroneously enter the ring; change the logic to require an
explicit self-vs-cross signal (e.g., expect a boolean like is_cross_attention or
is_self_attention passed via kwargs) and use that to immediately call
self.inner.forward(...) for cross-attention (instead of the shape check
k.shape[1] != q.shape[1]), and before entering the ring loop validate
attention_mask is either None or PredefinedAttentionMask.FULL and raise
NotImplementedError for any other mask (not just CAUSAL); update the code paths
around the symbols k.shape[1] != q.shape[1], PredefinedAttentionMask.CAUSAL,
self.inner.forward, and self.inner.forward_with_lse/_ring_send_recv so only true
self-attention with FULL/None mask runs the ring logic.
In `@tensorrt_llm/_torch/visual_gen/mapping.py`:
- Around line 38-40: Replace the non-ASCII multiplication character (×) used in
comments with an ASCII multiplication marker (either 'x' or '*') throughout
mapping.py; specifically update the comment lines that define "sp (sequence
parallelism) = cp × ulysses" and the following CP/attn examples (references:
symbols/sp, cp, ulysses, ring, attn2d, Attention2D) and the other occurrences
mentioned (around the blocks at 155-158, 243-247, 318) so ruff no longer flags
ambiguous Unicode—search for '×' and replace with 'x' or '*' in those comment
blocks.
In `@tensorrt_llm/_torch/visual_gen/utils.py`:
- Line 1: Add the standard NVIDIA SPDX header at the very top of the file (above
the existing module docstring """Utility functions for visual generation
pipelines."""), including the copyright line with the year of latest
modification (e.g., "Copyright (c) <YEAR>, NVIDIA CORPORATION & AFFILIATES") and
the SPDX license identifier "SPDX-License-Identifier: Apache-2.0"; ensure the
header is a multi-line comment block placed before the docstring so the file now
begins with the required NVIDIA/Apache-2.0 header.
- Around line 97-111: from_vgm() can return size>1 while group is None which
lets gather() call dist.all_gather(..., group=None) and accidentally use the
default world group; add a fail-fast invariant in the factory function
from_vgm() to raise a ValueError when size>1 and group is None (check vgm or the
derived group after computing size/rank/group) so sequence-parallel sharding
always requires a non-None group; reference the symbols from_vgm, vgm.seq_size /
size, group, gather, and dist.all_gather when locating and implementing the
check.
In `@tests/unittest/_torch/visual_gen/multi_gpu/test_ring_attention.py`:
- Around line 497-498: The docstring for class TestRingUlyssesAttention uses the
Unicode multiplication sign "×" which Ruff flags; update the docstring string
for TestRingUlyssesAttention to replace each "×" with ASCII "x" (e.g., change
"2×2 cp × ulysses" to "2x2 cp x ulysses") so linting passes while preserving the
original phrasing.
- Around line 44-59: The current try/except lumps optional FlashAttn4 imports
with required imports so an ImportError for FlashAttn4Attention sets
MODULES_AVAILABLE = False and skips non-FA4 tests; refactor by separating
required imports (PredefinedAttentionMask, RingAttention, UlyssesAttention,
AttentionTensorLayout, get_free_port) into their own try/except that controls
MODULES_AVAILABLE, then do a second optional try/except for FlashAttn4Attention
and _flash_attn_fwd that sets _fa4_fwd = None and FlashAttn4Attention = None on
failure and sets _flash_attn4_available = _fa4_fwd is not None, ensuring
RingAttention/UlyssesAttention tests run even if FA4 is absent.
In `@tests/unittest/_torch/visual_gen/multi_gpu/test_wan_ring.py`:
- Line 202: The test file has unused locals from unpacking _VIDEO_SHAPE and uses
a non-ASCII multiplication sign in docstrings; change the unpack to only keep
needed values (e.g., B, *_ = _VIDEO_SHAPE or B, *_rest = _VIDEO_SHAPE) or prefix
unused names with underscores (B, _C, _T, _H, _W = _VIDEO_SHAPE) to silence
Ruff, and replace any "2×2" docstring occurrences with the ASCII "2x2"; apply
the same fixes for the other occurrences referenced (the other unpack at the
same pattern and the docstring instances).
---
Outside diff comments:
In `@tensorrt_llm/_torch/visual_gen/attention_backend/flash_attn4.py`:
- Around line 171-186: The class defines support_lse(self) at the top but later
adds a misnamed supports_lse(cls) duplicate; remove or rename the incorrect
supports_lse method to support_lse (and avoid duplicate definitions) so the
class only implements the expected classmethod support_lse() used by the
codebase (refer to the methods support_lse and supports_lse in flash_attn4.py
and ensure the class uses support_lse matching AttentionBackend's interface).
In `@tensorrt_llm/_torch/visual_gen/attention_backend/interface.py`:
- Line 1: Update the copyright header in the file by changing the year portion
from "2025" to include 2026 (e.g., "2025-2026" or "2026" per project convention)
so the SPDX header reflects the latest modification year; edit the top-line text
that currently reads "Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES" to the
updated year string.
In `@tensorrt_llm/_torch/visual_gen/config.py`:
- Around line 61-104: The class docstring for ParallelConfig is inconsistent
about dit_ring_size: update the docstring to mark dit_ring_size as supported
(moving it out of the "Not Yet Supported" list or changing its line to
"Supported") so it matches the field comment and current behavior; locate the
ParallelConfig class docstring and change the bullet mentioning dit_ring_size
(previously under "Not Yet Supported") to reflect that dit_ring_size is
supported alongside dit_ulysses_size, or adjust wording to indicate supported vs
not supported features consistently with the dit_ring_size field.
In `@tensorrt_llm/_torch/visual_gen/mapping.py`:
- Around line 1-9: This file is missing the repository-required NVIDIA
SPDX/Apache-2.0 header; add the standard SPDX header and copyright/license block
at the top of tensorrt_llm/_torch/visual_gen/mapping.py so all new production
sources comply with the policy, keeping the rest of the module (including
VisualGenMapping, DeviceMeshTopologyImpl, build_mesh and the shared
DeviceMeshTopologyImpl.device_mesh) unchanged.
In `@tensorrt_llm/_torch/visual_gen/models/wan/transformer_wan.py`:
- Around line 1-9: This file missing the required NVIDIA copyright header; add
the standard NVIDIA copyright and Apache-2.0 license header comment block at the
very top of tensorrt_llm/_torch/visual_gen/models/wan/transformer_wan.py (above
the existing imports), with the correct year of latest modification and header
text that matches our repo template so it appears before the first symbol
(imports like math, torch, etc.) and ensures license metadata is present.
In `@tensorrt_llm/_torch/visual_gen/modules/attention.py`:
- Around line 1-6: Add the required NVIDIA copyright header and Apache-2.0
license notice at the top of the
tensorrt_llm/_torch/visual_gen/modules/attention.py file (above the existing
imports); include the latest modification year, the NVIDIA copyright holder
line, and the full Apache License, Version 2.0 boilerplate or SPDX identifier so
the file complies with the project's licensing header convention.
In `@tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py`:
- Around line 1-4: Add the standard NVIDIA SPDX header and Apache-2.0 notice to
the top of the modified test file
tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py: prepend
the repository-mandated copyright/license block (including the year of latest
modification and SPDX-License-Identifier: Apache-2.0) as used across other
source files, ensuring it appears before the module docstring and imports so the
file now contains the required header for VisualGenMapping tests.
---
Nitpick comments:
In `@tests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.py`:
- Around line 105-107: Add a test that exercises the new flattened sequence mesh
instead of only asserting _dim_names: instantiate
VisualGenMapping/SequenceSharder for a 4-GPU configuration (use world_size=4)
and verify that seq_rank is assigned following cp-major / ulysses-minor
linearization (i.e., seq_rank changes fastest across ulysses then cp), that
seq_group and ring_group are populated per the new API (seq_rank, seq_group,
ring_group fields on SequenceSharder), and assert that a collective over
seq_group spans cp_size * ulysses_size (use the SequenceSharder.cp_size and
.ulysses_size to compute expected group size). Ensure the test checks the happy
path mapping for all ranks (iterate ranks 0..world_size-1) rather than only
checking private _dim_names.
🪄 Autofix (Beta)
Fix all unresolved CodeRabbit comments on this PR:
- Push a commit to this branch (recommended)
- Create a new PR with the fixes
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📒 Files selected for processing (17)
examples/visual_gen/visual_gen_wan_t2v.pytensorrt_llm/_torch/visual_gen/attention_backend/__init__.pytensorrt_llm/_torch/visual_gen/attention_backend/flash_attn4.pytensorrt_llm/_torch/visual_gen/attention_backend/interface.pytensorrt_llm/_torch/visual_gen/attention_backend/parallel.pytensorrt_llm/_torch/visual_gen/config.pytensorrt_llm/_torch/visual_gen/mapping.pytensorrt_llm/_torch/visual_gen/models/flux/transformer_flux.pytensorrt_llm/_torch/visual_gen/models/flux/transformer_flux2.pytensorrt_llm/_torch/visual_gen/models/ltx2/transformer_ltx2.pytensorrt_llm/_torch/visual_gen/models/wan/transformer_wan.pytensorrt_llm/_torch/visual_gen/modules/attention.pytensorrt_llm/_torch/visual_gen/pipeline_loader.pytensorrt_llm/_torch/visual_gen/utils.pytests/unittest/_torch/visual_gen/multi_gpu/test_ring_attention.pytests/unittest/_torch/visual_gen/multi_gpu/test_visual_gen_mapping.pytests/unittest/_torch/visual_gen/multi_gpu/test_wan_ring.py
💤 Files with no reviewable changes (1)
- tensorrt_llm/_torch/visual_gen/pipeline_loader.py
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[sorry if i missed it] Did you add test coverage for Ring+Ulysses (Ring+Ulysses+CFG) combined?
Yes Ring+ulysses tests exist. I have added new tests for CFG+Ulysses+Ring |
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…ualGen (NVIDIA#13821) Signed-off-by: Venmugil Elango <498703+venmugil@users.noreply.github.com> Signed-off-by: Shreyas Misra <shreyasm@nvidia.com> Co-authored-by: Venmugil Elango <498703+venmugil@users.noreply.github.com>
…ualGen (NVIDIA#13821) Signed-off-by: Venmugil Elango <498703+venmugil@users.noreply.github.com> Signed-off-by: Shreyas Misra <shreyasm@nvidia.com> Co-authored-by: Venmugil Elango <498703+venmugil@users.noreply.github.com>
4 participants
WAN 2.2 14B perf on N GB200s -
Summary by CodeRabbit
New Features
--ring_sizeCLI argument to configure ring parallelismRefactor
Tests
Description
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PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
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