First discussed on zulip.
Quick summary: the set of what registers are available for inline assembly is related to the current target arch. However, the instruction_set attribute lets a function be compiled for what's effectively an alternate arch. This should allow the other arch's registers to be used, but currently that's not the case.
- Specifically for ARM a32/t32, the
thumb-mode target attribute is either not present (a32) or present (t32) in the target, and using the instruction_set attribute lets you have the opposite mode.
- Note: The actual assembly code is already compiled correctly on LLVM's side, it's just that rustc gives you the incorrect register class limits.
Quoting Amanieu's Zulip post on the probable fix for this:
You'd need to somehow remove the thumb-mode target feature from the list passed to the asm handling code in ast_lowering and intrinsicck when the containing function uses the a32 ISA.
First discussed on zulip.
Quick summary: the set of what registers are available for inline assembly is related to the current target arch. However, the
instruction_setattribute lets a function be compiled for what's effectively an alternate arch. This should allow the other arch's registers to be used, but currently that's not the case.thumb-modetarget attribute is either not present (a32) or present (t32) in the target, and using theinstruction_setattribute lets you have the opposite mode.Quoting Amanieu's Zulip post on the probable fix for this: