Special Reports

AI Raises The Bar For Tomorrow’s Engineers

By: Liz Allan

Universities are redesigning curricula and assessments around judgment, validation, and technical depth.
What Breaks When Packaging Moves From Wafer To Panel?

By: Gregory Haley

Engineers are discovering many things they thought were process assumptions were actually wafer assumptions.
Why Physical AI Is So Hard To Engineer

By: Brian Bailey

Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.

 more »

Top Stories

Fitting AI Models To Edge Applications

 Compression can shrink AI models, but efficient edge deployment starts with matching th...
November 5th, 2026 By Liz Allan

Physical AI Pushes The Limits Of Hardware

 Autonomous machines promise to transform industries, but memory bottlenecks, power cons...
November 5th, 2026 By Brendan Heffernan

College Grads And AI

 Computer science majors may be in an awkward space; EE grads are fine for now.
November 5th, 2026 By Brian Bailey

Shift Left Is Becoming A System-Level Problem

 Rise in complexity is pushing engineers to validate hardware, software, and physical co...
November 2nd, 2026 By Ed Sperling

Auto-Generation Of Properties: Methodology Insertion

 Technology is only useful if it improves an existing methodology. Property generation i...
October 29th, 2026 By Brian Bailey

Rethinking Shift Left In Chip Design

 Is it better to do everything earlier in the flow, or should design be more flexible an...
October 29th, 2026 By Ed Sperling

How Much Can Semiconductor Models Hide?

 Advanced packaging requires models to cross company boundaries without exposing proprie...
October 28th, 2026 By Gregory Haley

Bringing Down Test Costs For Co-Packaged Optics

 Pinpointing failures, ensuring known-good optical engines, and controlling test costs b...
October 26th, 2026 By Laura Peters

Chip Scaling Moves Beyond The Transistor

 SEMICON West 2026: Advanced packaging, photonics, test, and AI are increasingly intertw...
October 22nd, 2026 By Gregory Haley

Foundries And OSATs Increasingly Overlap

 Advanced packaging growth and capacity constraints are pushing more onto OSATs.
October 22nd, 2026 By Bryon Moyer

Scaling CPO Testing Beyond A Single Die

 Fiber alignment, connector durability, and simultaneous optical and electrical testing ...
October 21st, 2026 By Laura Peters

Why Open-Weight AI Matters

 Proprietary models still hold the edge, but open-weight models add more flexibility for...
October 15th, 2026 By Ann Mutschler

Agentic AI Alters The CPU-GPU Balance

 Agentic workloads increase CPU demand, while reasoning models, MoE architectures, and r...
October 15th, 2026 By Bryon Moyer

How Close Are We To Fully Autonomous Chip Design?

 Synopsys CEO Sassine Ghazi talks about AI agents, the limits of autonomous engineering,...
October 15th, 2026 By Ed Sperling

Why Heat Is Becoming A Bigger Chip Design Issue

 Increasing complexity requires thermal, electrical, and mechanical effects to be analyz...
October 14th, 2026 By Ed Sperling

Startup Funding: Q3 2026

 80 startups raised $8.5B in Q3, with big hauls by companies tackling data movement and ...
October 12th, 2026 By Jesse Allen

Shift Left Complicates Fab Data Management

 Streaming sensor data creates new challenges for advanced process control.
October 8th, 2026 By Anne Meixner and Laura Peters

CPO Testing Faces A Moving Target Problem

 Test vendors are adapting to changing connector architectures and extreme alignment tol...
October 8th, 2026 By Laura Peters

Thermal Complexity Grows With AI Chips And Photonics

 Increasing power density makes heat, stress, and aging harder to predict, and more crit...
October 7th, 2026 By Ed Sperling

Extreme Environments Push Chips To Their Breaking Point

 Orbital data centers, defense systems, quantum computing, particle physics, and advance...
October 5th, 2026 By Liz Allan

more top stories »

Latest News

Chip Industry Week In Review

 HBM smuggling routes into China; Nvidia H200s held in Hong Kong; Micron pauses Taiwan fab work; Samsung expands HBM base-die capacity; Oracle-Tencent AI chip deal...
November 6th, 2026 By The SE Staff

Blog Review: Nov. 4

 Chiplets for physical AI; rack-level considerations; verification complexity; sparse matrix workloads; AI data centers.
November 4th, 2026 By Jesse Allen

Chip Industry Week In Review

 Marvell to buy Lumentum; HBM shortages threaten AI expansion; TSMC weighs price hikes; advanced packaging ramps; domain-specialized AI models; Infineon and UMC bo...
October 30th, 2026 By The SE Staff

more news »



Perspectives & Analysis

Putting AI To The Test

 Who verifies the verifier? This is the age-old question for an...
November 2nd, 2026 By Brian Bailey

The imec Report: Scaling Optical Interconnects For The AI Era

 Unprecedented demand for bandwidth calls for bringing optics c...
October 27th, 2026 By Imene Jadli

more perspectives »



Research

Chip Industry Technical Paper Roundup: Nov. 3

 Meter-scale quantum interconnects; 2.5D/3D GPU integration and...
By Linda Christensen

Chip Industry Technical Paper Roundup: Oct. 27

 3D DRAM-on-GPU thermal design; multi-tier CFET self-heating an...
By Linda Christensen

Chip Industry Technical Paper Roundup: Oct. 20

 HBM power consumption; GAAFET leakage pathways; agentic AI for...
By Linda Christensen

more research »



Startup Corner

Startup Funding: Q3 2026

 80 startups raised $8.5B in Q3, with big hauls by companies ta...
By Jesse Allen

Moores Lab AI: Applying Agentic AI Across Chip Design

 EDA startup bets on domain expertise to speed the design process.
By Brendan Heffernan

more startups »

Videos

Accelerating Plug-And-Play Prototyping In Chiplet-Based Designs

November 4th, 2026

Scaling Data Movement For Physical AI

October 21st, 2026

Moving Test Data Faster

September 16th, 2026

The Intersection Of AI And Voice At The Edge

September 9th, 2026

Knowledge Centers / Entities, people and technologies explored

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy