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> Technical Papers
AI/ML/DL
Analog Superposition Increases Effective PCM Storage Density (IBM Research Europe)
Security-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland)
Neural Networks Speed 3nm Nanosheet SPICE Simulation (TU Munich)
Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)
Show More »
Architectures
Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)
Hardware Defense Blocks Memory-Dependent Prefetcher Leakage (KU Leuven)
Analog Superposition Increases Effective PCM Storage Density (IBM Research Europe)
Security-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland)
Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
Show More »
Automotive/ Aerospace
Thermal Side Channels Create New Security Risks For Autonomous Vehicles (Missouri S&T)
Formal Automotive Security Analysis Of CAN XL (Georgia Tech, QCRI, Purdue)
Chiplet Co-Design Framework Reduces Energy and Design Costs for AI Accelerators (University of Michigan)
Intrinsic Polarization Superjunctions Boost GaN-On-Silicon Power Devices (EPFL)
Hardware Abstraction Layer Study Targets Software-Defined Vehicles (U. of Stuttgart)
Show More »
Communication/Data Movement
Silicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA)
Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
Formal Automotive Security Analysis Of CAN XL (Georgia Tech, QCRI, Purdue)
Programmable Silicon Photonics Filter Enables Continuous Laser Wavelength Tuning (UiT, Stanford)
Hybrid Computing Framework Looks Beyond Peak TOPS/W For AI Efficiency (Nottingham Trent, ICL, Aston)
Show More »
Design & Verification
Co-Optimizing Access Points Improves Analog Placement (UT Austin)
Neural Networks Speed 3nm Nanosheet SPICE Simulation (TU Munich)
Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)
Agentic AI Automates RTL Waveform Analysis And Debugging (Columbia, Google)
Show More »
Lithography
Pt-W Alloy Shows Potential For Thinner High-NA EUV Mask Absorbers (Chinese Academy of Sciences et al.)
Dry-Deposited Resist Shows Different Tone Behavior Under EUV And E-Beam Exposure (KU Leuven, Kunsan, VUB, Imec)
Hyper-NA EUV: The Next Extension Beyond High NA Lithography (Carl Zeiss, ASML)
Molybdenum Quasi Phase-Only Masks Improve EUV Imaging (NYCU, TSMC)
Defect Prediction in Optical Lithography, EUVL, and NIL (National Taiwan University)
Show More »
Manufacturing
Pt-W Alloy Shows Potential For Thinner High-NA EUV Mask Absorbers (Chinese Academy of Sciences et al.)
Dry-Deposited Resist Shows Different Tone Behavior Under EUV And E-Beam Exposure (KU Leuven, Kunsan, VUB, Imec)
Carbon-Dot Interface Enables Ultrathin High-κ Dielectrics on 2D Semiconductors (UIUC, NETL, Argonne, Monash)
Deterministic Nucleation Enables Controlled Growth of 2D Semiconductors (KAIST, TDS, Hanyang et al.)
Hyper-NA EUV: The Next Extension Beyond High NA Lithography (Carl Zeiss, ASML)
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Materials
Fast, Sub-Volt HZO Ferroelectric Capacitors For DRAM-Like Memory (SNU)
Dry-Deposited Resist Shows Different Tone Behavior Under EUV And E-Beam Exposure (KU Leuven, Kunsan, VUB, Imec)
Carbon-Dot Interface Enables Ultrathin High-κ Dielectrics on 2D Semiconductors (UIUC, NETL, Argonne, Monash)
Deterministic Nucleation Enables Controlled Growth of 2D Semiconductors (KAIST, TDS, Hanyang et al.)
Reducing Contact Resistance Pushes 2D Transistors Toward Advanced CMOS (HUST, PolyU, UCSB, NUS)
Show More »
Memory
Fast, Sub-Volt HZO Ferroelectric Capacitors For DRAM-Like Memory (SNU)
Analog Superposition Increases Effective PCM Storage Density (IBM Research Europe)
Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)
Security-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland)
Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)
Show More »
Optoelectronics / Photonics
Silicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA)
Ultra-Compact Photonic Bends Reduce Loss While Meeting Foundry Rules (Georgia Tech)
Programmable Silicon Photonics Filter Enables Continuous Laser Wavelength Tuning (UiT, Stanford)
Ferroelectric Tuning Reduces Optical-Interconnect Stalls In LLM Training (Georgia Tech)
Rapid Switching of Optical Properties in a Doped Semiconductor By Femtosecond Laser Pulses (Imperial College London, U. of Exeter)
Show More »
Packaging
AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE)
3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB)
Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)
A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)
Monolithic 3D Memristor-TFT Stack For Programmable Neuromorphic Computing (SNU, Yonsei)
Show More »
Power & Performance
Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)
Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)
Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)
Characterization of HBM Power Consumption (ETH Zurich, NYU)
Show More »
Quantum
Quantum Interconnects Link Two 120-Qubit Processors (IBM Research)
Room-temperature, CMOS-compatible Photonic Quantum Processor (NUS et al.)
Mapping and Routing Fault-Tolerant Quantum Circuits Onto Chiplet Architectures (TU Munich)
Simulations of Silicon Spin Qubits Based on a GAAFET (Teikyo U., Riken)
A Manufacturing Approach That Brings Diamond Quantum Photonics Closer To Industrial Production (MIT, KAUST et al.)
Show More »
Security
Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)
Hardware Defense Blocks Memory-Dependent Prefetcher Leakage (KU Leuven)
Security-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland)
Thermal Side Channels Create New Security Risks For Autonomous Vehicles (Missouri S&T)
On-Chip Monitors Detect Bit-Flip Attacks in AI Accelerators (UF, UT Dallas, RPI)
Show More »
Test, Measurement, Analytics tech papers
AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE)
Molecular Dynamics Study Explains Aluminum Dopant Activation In 4H-SiC (TU Wien, Silvaco)
Deep Learning Automates Parameter Extraction For 2D Transistors (Stanford, SLAC)
Defect Prediction in Optical Lithography, EUVL, and NIL (National Taiwan University)
Failure Analysis HW Enables System-Level Debug For 3D ICs (Google, TU Delft)
Show More »
Transistors
Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)
Neural Networks Speed 3nm Nanosheet SPICE Simulation (TU Munich)
Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)
Simulations Pinpoint Leakage Pathway In GAAFETs (Sandia, Luxembourg)
Carbon-Dot Interface Enables Ultrathin High-κ Dielectrics on 2D Semiconductors (UIUC, NETL, Argonne, Monash)
Show More »
Z-End Applications
Energy-Aware DL: The Interplay Between NN Efficiency And Hardware Constraints (Imperial College London, Cambridge)
Overview Of Printed And Flexible Electronics: Technology Fundamentals, Design And Practical Applications
In-Depth Study of Low-Power MCUs For Wearables (EPFL)
Flexible IGZO RISC-V Microprocessor
Scalable Fabrication of Graphene FETs on Non-Planar Surfaces (Imperial College London)
Show More »
Technical Papers By Date
Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)
- 11-26
Fast, Sub-Volt HZO Ferroelectric Capacitors For DRAM-Like Memory (SNU)
- 11-26
AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE)
- 11-26
3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB)
- 11-26
Quantum Interconnects Link Two 120-Qubit Processors (IBM Research)
- 11-26
Hardware Defense Blocks Memory-Dependent Prefetcher Leakage (KU Leuven)
- 11-26
Co-Optimizing Access Points Improves Analog Placement (UT Austin)
- 11-26
Analog Superposition Increases Effective PCM Storage Density (IBM Research Europe)
- 10-26
Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)
- 10-26
Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)
- 10-26
Show More »
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