[dev test] 62256 — FAIL (18ef81797b1a) #83

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1. dim20 commented on Sep 15, 2026

   

   dim20

   on Sep 15, 2026

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   I ran this dev test using the generic 62256 profile. The physical chips in the socket are LinkSmart LST62832I-70LL (32K x 8-bit SRAM). I have attached the related datasheet which confirms it uses a completely standard 5V, 28-pin layout.

   The test failed, and the same behavior is witnessed across 4 identical chips from this batch.

   The logs consistently show:
   Verify failed: Expects 0xff but reads 0x00 at address 0x000000.

   Read divergence: The read step completes, but the runs diverge at a single byte (e.g., offset 2048), meaning it reads different data from the same address on consecutive passes.

   LST62832I.PDF
2. henols commented on Sep 16, 2026

   

   henols

   on Sep 16, 2026

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   Datasheet cross-check — 62256 (LinkSmart LST62832)

   Thank you for naming the physical part and attaching its datasheet, @dim20 — and for the
   detail that four chips from the batch behave identically. That last point does most of the
   work here: it rules out a failing device, which is normally the first thing to suspect.

   Datasheet: LinkSmart LST62832, 32K × 8 5 Volt CMOS Static RAM (preliminary, rev A), the PDF
   attached above.
   Failing step: verify BAD

   Check	Datasheet	Database	Verdict
   Pin map (28-DIP)	p. 3, 28-Pin PDIP: 1=A14, 2=A12, 3=A7, 4=A6, 5=A5, 6=A4, 7=A3, 8=A2, 9=A1, 10=A0, 11–13=I/O0–2, 14=GND, 15–19=I/O3–7, 20=CE, 21=A10, 22=OE, 23=A11, 24=A9, 25=A8, 26=A13, 27=WE, 28=VCC	DIP28_28C256 (rw-pin: [27])	MATCH — all 28 pins agree
   Size	32,768 words × 8 bits	0x8000	MATCH
   VCC	single 5 V ± 10%	vcc_mv: 5000	MATCH
   Type / blank state	volatile SRAM — no factory-blank state	SRAM; blank-check correctly NA	MATCH
   Chip ID	none — SRAM publishes no signature	chip_id_check: false	MATCH — id correctly NA
   Erase	not applicable to SRAM	erase NA	MATCH
   Write protection	none	protect_off_before/protect_on_after: false	MATCH
   Pulse timing	70 ns part; WE controls the write cycle	pulse_duration_us: 0	see below

   Nothing describing the part is wrong. The pin map is right down to WE on pin 27, the size
   is right, the supply is right, and the three NA steps are all correctly NA. So this is not a
   database fault, and it is not the socket.

   One correction to the reading, which changes what it means. The verify line is
   0x00 != 0xff at 0x000000, and the firmware packs that message expected first, actual
   second (MSG_ERR_VERIFY, format "0x%02x != 0x%02x at 0x%06x", emitted in
   memory_verify_execute as {expected, byte, addr…}). So the harness expected 0x00 at
   address 0 and read back 0xff — the opposite way round from "expects 0xff but reads 0x00".
   That matters: 0xff at address 0 is the signature of a bus that is not returning written data,
   not of a device stuck at zero.

   Why write: OK is not evidence that the write worked. memory_write_execute is a bare
   loop — it calls firestarter_set_data for each byte and returns. It has no error path at
   all, so it cannot report a failure under any circumstances. The step's OK verdict means
   "the loop ran to completion", not "the data landed". The first real oracle in this plan is
   verify, and it failed at the first byte it looked at.

   Where I think the fault is. Protocol 40 dispatches to configure_sram(), and that function
   is a stub — its entire body is a debug log line:

   void configure_sram(firestarter_handle_t* handle) {
       LOG_DEBUG_ID_SUB(DBG_CONFIGURING_SRAM);
   }

   It binds no handlers and configures nothing, so an SRAM run inherits only the generic
   configure_memory path, which was built around EPROM/EEPROM programming. Two consequences
   follow directly:

   1. The write strobe has no specified width. memory_set_data drives a cycle as
      rurp_chip_enable() → mem_util_delay_us(handle->pulse_delay) → rurp_chip_disable().
      For this part the database supplies pulse_duration_us: 0, and mem_util_delay_us(0)
      splits to ms = 0, rem = 0 and therefore delays for nothing at all. Enable and disable are
      back to back.
   2. Nothing protocol-specific sets up the WE line for an SRAM write cycle. The control
      register has a CTRL_READ_WRITE bit (0x040) and the pinout does map rw-pin to pin 27,
      so the line exists — but configure_sram() is where a protocol would arrange to drive it,
      and it does nothing.

   The read-step divergence you describe fits the same picture: two passes over the same
   addresses returning different bytes at a single offset is what an under-driven or
   under-timed bus looks like, not what a healthy 70 ns SRAM does.

   Most likely cause: SRAM support is unimplemented rather than broken — protocol 40 is
   registered and reachable, but its handler is empty, so writes go out through a generic path
   with a zero-width strobe and reads come back unreliable. I have not put a scope on it, so the
   WE half of that is reasoned from the source rather than measured, and it is the first thing to
   confirm.

   Secondary, and worth fixing on its own: a write step that is structurally incapable of
   reporting failure will keep producing reports that look half-successful. That is a harness
   issue independent of whatever the firmware does.

   Unchecked: nothing in the table — your datasheet covers every row. What is not established
   is the electrical behaviour at the socket; that needs a bench measurement, not a datasheet.
3. henols

   added

   dev-testCommunity `dev test` chip-validation reportCommunity `dev test` chip-validation report

   cause:firmwareDefect in the Arduino firmwareDefect in the Arduino firmware

   cause:harnessDefect in the `dev test` harness itselfDefect in the `dev test` harness itself

   on Sep 16, 2026
4. henols commented on Sep 16, 2026

   

   henols

   on Sep 16, 2026

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   One targeted follow-up, @dim20 — and deliberately a small one, because most of
   this issue does not need another run from you.

   What does not need re-testing. The cross-check above concluded that SRAM
   support is unimplemented rather than broken: protocol 40 is registered and
   reachable, but configure_sram() does nothing and nothing arranges the WE line
   for an SRAM write cycle. If that reading is right, re-running write and
   verify on a newer build will fail exactly as it did — there is no fix between
   3.0.0b44 and the current 3.0.0b45 aimed at this, and reporting the same
   verify BAD 0x00 != 0xff at 0x000000 again would not add anything.

   The one thing that would genuinely help. Your report recorded read OK but
   with the runs diverging — two passes over the same addresses returning
   different bytes. That part is not explained by an empty write handler, and it
   is the piece I am least sure about. If it reproduces, it points at the bus
   timing on the read path; if it does not, it was a one-off and the write-side
   analysis stands alone.

   So if you have the rig set up anyway:

   pip install --pre -U firestarter     # 3.0.0b45
   firestarter fw --install             # 3.0.0b31
   firestarter dev test 62256
   

   and tell me whether the read step diverges again. Post it even if the overall
   verdict is still FAIL — that is the expected outcome here, and the read-step
   behaviour is the signal I am after, not the headline verdict. Reports now
   capture the firmware and host log lines per step, which will show more than the
   previous run did.

   If you would rather not spend another 5 minutes on a part whose support is
   unimplemented, that is entirely reasonable — say so and I will treat the read
   divergence as unconfirmed and note it as such.
5. henols

   added

   needs:reportWaiting on a fresh `dev test` run from the reporterWaiting on a fresh `dev test` run from the reporter

   on Sep 16, 2026
6. dim20 commented on Sep 17, 2026

   

   dim20

   on Sep 17, 2026

   Author

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   canonical part number: 62256
   elapsed: 59.5s

   Step	Verdict	Runs	Took	Error	Reason
   id	NA	-	-	-	-
   read	OK	2	22.2s	-	read runs diverged
   blank-check	NA	-	-	-	-
   write	OK	1	30.9s	-	-
   verify	BAD	1	3.25s	MSG_ERR_VERIFY (175)	0x00 != 0xff at 0x000000
   erase	NA	-	-	-	-
   write-baseline-b	NA	-	-	-	-
   write-baseline-a	NA	-	-	-	-
   sdp-lock	NA	-	-	-	-
   write-inhibited	NA	-	-	-	-
   sdp-unlock	NA	-	-	-	-
   write-restored	NA	-	-	-	-

   captured log lines (captured=21, dropped=0, truncated=0):

   [-] firmware ERROR: ERROR: Empty input (x2)
   [read] firmware ERROR: ERROR: Empty input (x4)
   [write] firmware ERROR: ERROR: Empty input (x10)
   [verify] firmware ERROR: ERROR: Empty input (x2)
   [verify] firmware ERROR: ERROR: 0x00 != 0xff at 0x000000
   [verify] host ERROR: Programmer error during VERIFY: 0x00 != 0xff at 0x000000
   [verify] host ERROR: Verify for 62256 failed.
   

   {
     "schema_version": "2.2",
     "generated": "2026-09-17T10:46:07Z",
     "elapsed": 59.452,
     "auto_capture": {
       "host_version": "3.0.0b45",
       "fw_board_identity": "3.0.0b31:uno",
       "hw_revision": "Rev 2.0-class",
       "chip": "62256",
       "protocol": "40",
       "chip_id_expected": null,
       "chip_id_actual": null,
       "chip_id_mismatch_reason": null,
       "canonical_part_number": "62256"
     },
     "transport_health": {
       "cobs_errors": "not measured",
       "crc_failures": "not measured",
       "decode_failures": 0,
       "probe_timeouts": 0,
       "resync_body_truncated": 0,
       "resync_length_missing": 0,
       "retries": "not measured",
       "timeouts": 0,
       "transport_suspect": false
     },
     "steps": [
       {
         "op": "id",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "read",
         "verdict": "OK",
         "status": "COMPLETE",
         "run_count": 2,
         "reason": "read runs diverged",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": {
           "repeat_divergent": true,
           "cmp_len": 32768,
           "bad": 2,
           "pct": 0.006103515625,
           "first_offset": 2048
         },
         "chip_id_detected": null,
         "duration_s": 22.179,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "blank-check",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "write",
         "verdict": "OK",
         "status": "COMPLETE",
         "run_count": 1,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": 30.925,
         "write_region_start": 0,
         "write_region_length": 32768,
         "write_bits_cleared": 0,
         "write_bits_retained": 0,
         "write_current_source": "address-derived pattern (unmasked)",
         "write_coverage": null
       },
       {
         "op": "verify",
         "verdict": "BAD",
         "status": "COMPLETE",
         "run_count": 1,
         "reason": "0x00 != 0xff at 0x000000",
         "error_code": 175,
         "error_name": "MSG_ERR_VERIFY",
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": 3.25,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "erase",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "write-baseline-b",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "write-baseline-a",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "sdp-lock",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "write-inhibited",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "sdp-unlock",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       },
       {
         "op": "write-restored",
         "verdict": "NA",
         "status": "SKIP",
         "run_count": 0,
         "reason": "",
         "error_code": null,
         "error_name": null,
         "fingerprint": null,
         "fingerprint_total": null,
         "fingerprint_bad": null,
         "fingerprint_bad_pct": null,
         "fingerprint_evidence": null,
         "divergence": null,
         "chip_id_detected": null,
         "duration_s": null,
         "write_region_start": null,
         "write_region_length": null,
         "write_bits_cleared": null,
         "write_bits_retained": null,
         "write_current_source": null,
         "write_coverage": null
       }
     ],
     "banner": {
       "n_ran": 3,
       "m_applicable": 3
     },
     "voltage": {
       "vpp_before_mv": 12400,
       "vpp_after_mv": 12400,
       "vpe_before_mv": 14500,
       "vpe_after_mv": 14500
     },
     "is_submittable": true,
     "dedup_fingerprint": "18ef81797b1a",
     "db_diff": {
       "current_support_status": "supported",
       "proposed_disposition": "suggests: community-fail signal (advisory -- human triage required)",
       "ladder_state": "community-fail"
     },
     "sdp_hold_state": "NOT-RUN",
     "run_status": "COMPLETE",
     "is_uv": false,
     "rail_reading_disclosure": "vpp/vpe readings measure the regulator rail only -- they do not show whether the eprom socket is connected (advisory)",
     "log_capture": {
       "entries": [
         {
           "step": null,
           "source": "firmware",
           "level": "ERROR",
           "message": "ERROR: Empty input",
           "repeat": 2
         },
         {
           "step": "read",
           "source": "firmware",
           "level": "ERROR",
           "message": "ERROR: Empty input",
           "repeat": 4
         },
         {
           "step": "write",
           "source": "firmware",
           "level": "ERROR",
           "message": "ERROR: Empty input",
           "repeat": 10
         },
         {
           "step": "verify",
           "source": "firmware",
           "level": "ERROR",
           "message": "ERROR: Empty input",
           "repeat": 2
         },
         {
           "step": "verify",
           "source": "firmware",
           "level": "ERROR",
           "message": "ERROR: 0x00 != 0xff at 0x000000",
           "repeat": 1
         },
         {
           "step": "verify",
           "source": "host",
           "level": "ERROR",
           "message": "Programmer error during VERIFY: 0x00 != 0xff at 0x000000",
           "repeat": 1
         },
         {
           "step": "verify",
           "source": "host",
           "level": "ERROR",
           "message": "Verify for 62256 failed.",
           "repeat": 1
         }
       ],
       "captured": 21,
       "dropped": 0,
       "truncated": 0,
       "max_entries": 20,
       "max_line_chars": 160
     }
   }
7. dim20 commented on Sep 17, 2026

   

   dim20

   on Sep 17, 2026

   Author

   More actions

   I ran the test on host 3.0.0b45 and firmware 3.0.0b31 as requested.

   To answer the main question: Yes, the read divergence reproduced identically.

   This would confirm your suspicion: the bus timing on the generic read path is likely under-driven or mis-timed for this SRAM.

   Let me know if you need any other tests once you start implementing the SRAM protocol.
8. henols

   added a commit that references this issue on Oct 10, 2026

   chore: point the gitlinks at the sub-repo main merges (app #90, fw #83)

   cbdfd4e