Power Control Circuit

I’m designing a power control front-end for a 48 V (60 V max) system using the LM5069 hot-swap controller. My goal is to implement a press-to-turn-on / MCU-latch-ON / MCU-kill-power sequence using only an SPST momentary switch and a few BJTs.

Circuit Intent (High-Level)

• Default state = OFF When battery is connected, LM5069 must remain OFF until the user presses the button. As per LM5069 datasheet - if the UVLO/EN is pulled to ground it will get shutdown and if the voltage is above 2.5V, it will Turn ON.

• Single SPST button performs:

• At startup: user presses the switch → enables LM5069 → 3.3 V rail comes up

• After system is ON: subsequent presses must be detected by MCU (as a digital input) without affecting power

• MCU latch ON: As soon as 3.3 V comes up, a BJT latch should hold UVLO released even after the user stops pressing the button.

• MCU kill: MCU should be able to pull a “kill” signal which forces UVLO low, shutting off LM5069 and keeping it OFF until the button is pressed again.

How the Circuit Supposed to work

• Let's use Node A = junction of R52, R53, R54, R55
• Node B = junction of R55, Q7 base, Q8 collector.

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1. Power-up (no 3.3 V available) : LM5069 OFF By default

• Node A is pulled high from +48 V via R52 470 k resistor. Node B (Q7 base) also rises.

• Q7 turns ON → pulls UVLO low → LM5069 stays OFF.

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2. User presses SW1 (momentary to GND)

• SW1 pulls Node A to GND through a 1 k resistor.
• Node B also goes low.
• Q7 turns OFF → UVLO rises to its divider voltage → LM5069 turns ON → external MOSFET switches 48 V to the DC-DC converter → 3.3 V rail powers up.

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3. The 3.3 V comes up → latch engages (Q8 + Q9 block)

• On power-up, MCU pin is low, so Q9 is OFF.
• Q8 receives 3.3 V through a 10 k / 470 Ω network and turns ON
• Q8 clamps Node B to GND, keeping Q7 OFF even after SW1 is released.

The system is now latched ON.

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4. SW1 used later as a user-input (Q6)

• Q6 senses Node A through 470 k and inverts it into the MCU input.
• SW1 not pressed: Node A ≈ high → Q6 ON → MCU sees LOW
• SW1 pressed: Node A pulled low → Q6 OFF → MCU sees HIGH

This allows the MCU to react to button presses (e.g., enable Bluetooth, change mode) without altering the power latch.

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5. MCU kill sequence (Q9)

• MCU sets PWR_KILL_SIG high → Q9 turns ON..
• Q9 pulls Q8’s base low → Q8 turns OFF
• Q9 pulls Q8’s base low → Q8 turns OFF
• Node A is high (button not pressed), so Q7 turns ON → pulls UVLO low.
• LM5069 shuts off and power collapses.
• When 3.3 V disappears, Q8/Q9/Q6 all turn OFF; Node A & B float high again, keeping Q7 ON.

System stays OFF until the user presses SW1 again.

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Questions

1. Does the soft-latch mechanism around UVLO (Q7/Q8/Q9 network) look electrically sound for reliably turning LM5069 ON and OFF?
2. Is the timing margin sufficient to ensure that LM5069 stays ON long enough for 3.3 V to rise and for Q8 to engage the latch?
3. Any concerns about sensing Node A (48 V derived) using a high-value resistor (470 k) into a BJT inverter? Are leakage currents or noise an issue here?
4. Node A and Node B rise toward ~48–60 V through large resistances. Are the transistor base-emitter junctions safe in this configuration, or should I add a small zener clamp (e.g., 5.1 V) to Node B for protection?
5. The SW1 line will be floating when switch is released, should I add a pull down 100K before R54 ?
6. How do I make sure when MCU turns ON, it won't kill the circuit or when I am programming I don't power to cutoff because of GPIO reset.
7. What will be current consumption when LM5069 is OFF? I need uA current draw in standby mode.