Ripple calculation for Powering ADC
This a continuation of my previous question. As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit ADC. Olin suggested me to add filtering at the output of the Buck-Boost converter. My circuit diagram is given below.
Output waveforms and measured ripple voltage are shown below.
DVDD & IOVDD Rail:
I am getting a ripple voltage of 7.5 mV Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
AVDD Rail:
Here you can see that I am getting ripple of 8 mV peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = ≈50 µV. The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=50 mV.
My measured ripple voltage at the powerline is 8 mV Peak-Peak.
Therefore the Ripple at ADC = (8 mV) / 1000 = 8 uV.
So I believe,I can go ahead with this design. May I know your thoughts.
Update:
In the previous simulation I have considered ESR of Capacitor only and the ESR I selected is 0.004 Ohm. In the below results I considered the ESR of Inductor (MSS4020-103ML) also and it is 0.21 Ohm. Please see the results below.
In the digital rail I am getting a ripple of 41.4 mV (Peak to Peak) and in the analog rail I am getting a ripple of 38 mV (Peak to peak).
DVDD & IOVDD :
AVDD:
May I know Can I go with BUCK-BOOST solution.
Or Do I need to go with BUCK-BOOST + LDO Solution.
1 answer
The following users marked this post as Works for me:
| User | Comment | Date |
|---|---|---|
| newbie | (no comment) | Dec 21, 2025 at 11:41 |
I already answered some of this two weeks ago to your question Powering ADC using Buck Boost Converter.
I did not say to filter the output directly from the buck/boost converter, only to the A/D. As I said before, the digital chips will be fine with a few 10s of mV ripple.
Your plots are hard to see. They mostly look like black blobs, so I ignored them.
Enough with the simulator! Try using your brain, and testing.
Simulators can be useful for verifying the general topology. But there will always be details you can't enter into the simulation. Start by actually thinking about the circuit. Ultimately you will have to do real testing when things like parasitic capacitance and inductances, non-ideal characteristics, and ground bounce matter, as they do in this case.
You mean the filtered output should only be provided to AVDD?
As I said, the digital chips will be fine with a few 10s of mV ripple on the supply. You also don't want the digital chips to pollute the analog power you just carefully filtered to create. Carefully filtered analog power should only be used by those parts that actually need it.
A separate point I meant to address but missed earlier:
The internal reference has ~60 dB PSRR
Internal reference of what, the LDO you are considering or the A/D? In either case, this is probably not as useful as you think. Look at the datasheet carefully and check at what frequency the 60 dB PSRR (power supply rejection ratio) applies. The PSRR at 100 kHz or whatever your switching frequency is quite likely less, probably a lot less.
Unless the datasheet explicitly says it's OK, I wouldn't want the switching noise directly connected to the A/D. You can make an external filter that you know will attenuate the switching noise to tolerable levels. Without explicit information in the datasheet about PSRR over frequency, you don't know what you might get.
Another issue is do you really need 16 bits? What are you trying to measure? What are other sources of noise? How fast will you be sampling?
If the measurement is ratiometric to the supply, then some supply noise below the Nyquist frequency will cancel out.
You need to look at the whole system.
How fast will you be sampling?--> I need to check with the firmware team.
do you really need 16 bits? --> Frankly speaking I don't know that, I am tasked to do the hardware.
No! You have been tasked to do engineering. That includes making sure what you design solves the problem, not just follows some vague description.
If you are not given proper specs, then it is your job to get them. That can be as simple as asking more questions. Other times you have to start with the problem the circuit is supposed to solve, then synthesize the specs from that. In that case, you feed back the final performance, cost, and other parameters back to the customer and have them sign off on them. Only then are you ready to "do the hardware".
In any case, there is no substitute for you understanding what the overall problem is and how your circuit fits into that. Even if you are handed a good set of specs, it is still your job to verify that a circuit that meets those specs would actually solve the problem.
You should also assume the customer is not aware of all possible tradeoffs. As you get into the preliminary design, you might see options that could make things faster, cheaper, easier to manufacture, etc, if only a few requirement were relaxed a little. It is your job to verify whether those requirements are really needed as stated, and if not, present options and recommendations back to the customer.
For example, using a 16 bit A/D comes with some burden to use properly. The customer might have specified 16 bits because they heard somewhere that it's "high quality". The first thing you should have done was verify that 16 bits was really needed, and if not, get back to the customer and explain how using a 12 bit A/D (for example) built into a microcontroller would simplify things without loss of features.
Getting this far into a design and not knowing why 16 bits is required, or not knowing if it is, is downright irresponsible!
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