Naveen Jakhar, I.T.S.

In our country, a mobile subscriber purchases a new SIM or takes a new mobile connection by submitting his/her proof of identity (PoI) and proof of address (PoA) along with the customer acquisition form (CAF) having his passport sized photograph and prescribed application fee at the point of sale of any telecom service provider (TSP). The PoS executive hands over the SIM to the mobile subscriber. Then the tele-verification of the mobile subscriber is done by TSP executive. If the… Show more

In our country, a mobile subscriber purchases a new SIM or takes a new mobile connection by submitting his/her proof of identity (PoI) and proof of address (PoA) along with the customer acquisition form (CAF) having his passport sized photograph and prescribed application fee at the point of sale of any telecom service provider (TSP). The PoS executive hands over the SIM to the mobile subscriber. Then the tele-verification of the mobile subscriber is done by TSP executive. If the tele-verification is successful, the mobile subscriber’s SIM is activated by TSP and he/she starts using the SIM. This is the routine procedure we all follow while purchasing a new SIM. But do you know one thing? As an aware and responsible customer, you must take the receipt from the PoS executive when you are submitting your documents (i.e. PoA and PoI) and application form for purchasing a new SIM. What if the PoS executive denies to give you the receipt? Do we have any law for this? In this article, we shall be presenting the importance of this receipt and try to provide answers to the above mentioned questions. Show less

Today's mobile phone market is flooded with smartphones having unimaginable capabilities like multicore processors running in tandem, primary and secondary cameras supporting up to 20-25 Megapixels with dual LED flash, expandable memories up to 256 GB and up to 6 GB RAM for providing multiprocessing capabilities like simultaneously playing video games, Internet surfing, and watching online videos, social media, etc. Every one of us chooses the phone with best returns-on-investment and best… Show more

Today's mobile phone market is flooded with smartphones having unimaginable capabilities like multicore processors running in tandem, primary and secondary cameras supporting up to 20-25 Megapixels with dual LED flash, expandable memories up to 256 GB and up to 6 GB RAM for providing multiprocessing capabilities like simultaneously playing video games, Internet surfing, and watching online videos, social media, etc. Every one of us chooses the phone with best returns-on-investment and best features. But apart from these selling parameters of any mobile device, we should also concentrate on other important parameters which are related to phone information, IMEI number, battery information, and SAR (specific absorption rate) values violating international standards set for mobile manufacturing. In this article, we shall be discussing all these parameters and the importance of each parameter. The aim of this article is to create awareness amongst end users of mobile devices.
Link in the offline mode of magazine:
http://www.communicationstoday.co.in/ezine/ Show less

As a result of increasing complexity of the VLSI designs, SoC verification engineers are shifting their focus towards SoC level verification involving real use-case scenarios. These use-cases are the replica of how the SoC will be used by the customers in field. So, it involves verification of multiple IPs working in tandem. Along with the increasing number of IPs being used in an SoC for performing multitudes of operations, VLSI designers are designing SoCs with advanced clocking and reset… Show more

As a result of increasing complexity of the VLSI designs, SoC verification engineers are shifting their focus towards SoC level verification involving real use-case scenarios. These use-cases are the replica of how the SoC will be used by the customers in field. So, it involves verification of multiple IPs working in tandem. Along with the increasing number of IPs being used in an SoC for performing multitudes of operations, VLSI designers are designing SoCs with advanced clocking and reset architectures, multiple mode of operations, support for exit from low power modes using internal/external wakeups and interrupts etc. for being the frontrunners in the field of innovation. So, along with covering the functional operations of the SoC, the use-case needs to cover two important aspects:

The impact of changing clock configurations and modes of operations, abnormal clock failure, interrupts, resets and wakeups being generated at any time.
How does the SoC recover after the generation/occurrence of these events?
So, we need to create an intelligent and dynamic test suite, based on certain parameters defined in Architecture Design Document (ADD) and SoC guide, which can be used as a backbone for creating robust use-cases. The parameters like number of system clocks and their frequencies, different types of resets, interrupts, wakeups and modes of operations are used to create all the possible combinations of operations and events which can affect the operations of a given SoC. In this article, we will be highlighting the needs and advantages of this kind of Integrated Low Power Verification Suite. Show less

The next generation SoCs are supporting multi-power domains and multi- mode operations features for supporting aggressive operational functionality and reduced power numbers. There are various asynchronous events like external resets, external interrupts, external wakeups, clock failures etc. which might occur during the windows of ongoing mode transitions in the actual use-case scenario of the SoC. So, the combination of these events during mode transitions bring an entropy and uncertainty in… Show more

The next generation SoCs are supporting multi-power domains and multi- mode operations features for supporting aggressive operational functionality and reduced power numbers. There are various asynchronous events like external resets, external interrupts, external wakeups, clock failures etc. which might occur during the windows of ongoing mode transitions in the actual use-case scenario of the SoC. So, the combination of these events during mode transitions bring an entropy and uncertainty in the design which needs to be thoroughly verified. The conventional SoC level verification approach for these asynchronous events does not cover how these events are going to affect the mode transitions. Even addition of randomization of these events during mode transitions does not provide fool proof solution. In this article, we will be highlighting the grey areas and corner case bugs which are reported by the customers when they use these SoCs in their actual use-cases and how to do the robust verification of the corner case scenarios during pre-silicon SoC verification using Corner Case Scenario Generation Tool. Show less

Today’s SoC designers are designing chips which have an optimum balance between performance and power numbers. So, the whole SoC design is divided into different power domains having a set of modules present in each of them. The power domains can be kept powered-on in some modes of operations and can be power gated in some other modes of operations. When a power domain is disconnected from the power supply, the power consumption is reduced to zero in that domain and all the modules in that… Show more

Today’s SoC designers are designing chips which have an optimum balance between performance and power numbers. So, the whole SoC design is divided into different power domains having a set of modules present in each of them. The power domains can be kept powered-on in some modes of operations and can be power gated in some other modes of operations. When a power domain is disconnected from the power supply, the power consumption is reduced to zero in that domain and all the modules in that power domain are power-gated off. It helps in claiming reduced power numbers but it has an adverse effect also. Any status information of such a power domain is lost. So, the ultimate goal is to reduce the power numbers while keeping the functionality of SoC intact. The modules which are power gated need to be in reset state to avoid any malfunctioning inside SoC and to avoid leakage currents. Thus, for complex SoCs having multiple power domains, a need arises for robust verification of reset connectivity of central reset generation module to different modules present in different power domains. In this paper, we will be presenting some potential issues in reset connectivity and an automated verification scheme for the same. Show less

Session VER2.202 : A Novel Approach for Low Power Verification Using Randomization on a Given Power and Clocking Matrix :
With the growing complexity of SoCs, multiple clock sources are available to support the design. Moreover depending upon the power and functionality requirements, we can have different power modes in SoCs. The challenge is to verify all the clock sources’ configurations in all modes by sweeping past across all modes and having different clock configurations in each mode… Show more

Session VER2.202 : A Novel Approach for Low Power Verification Using Randomization on a Given Power and Clocking Matrix :
With the growing complexity of SoCs, multiple clock sources are available to support the design. Moreover depending upon the power and functionality requirements, we can have different power modes in SoCs. The challenge is to verify all the clock sources’ configurations in all modes by sweeping past across all modes and having different clock configurations in each mode. We need to cover m*(2^n)*p cases, where m is the number of power modes, n is the number of clock sources and p is the number of possible system clock sources. It will be very tedious to cover all these possible combinations by directed test cases. In this session, an approach, based on the concept of adjacency matrices, is presented in which clocking and mode verification has been done together using randomization which provides full coverage for the valid combinations. Show less

Cache, in its crude definition, is a faster memory which stores copies of data from frequently used main memory locations. Now a days multiprocessor systems are supporting shared memories in hardware. Now the question arises how can these different processors share each other’s caches? The answer is Cache Coherency. Shared memory systems implement a coherence protocol for this purpose. Coherency seeks to make the caches of a shared-memory system functionally available to all the processors. In… Show more

Cache, in its crude definition, is a faster memory which stores copies of data from frequently used main memory locations. Now a days multiprocessor systems are supporting shared memories in hardware. Now the question arises how can these different processors share each other’s caches? The answer is Cache Coherency. Shared memory systems implement a coherence protocol for this purpose. Coherency seeks to make the caches of a shared-memory system functionally available to all the processors. In this paper, we present the efficient checks for Cache Coherency verification in Complex SoCs having multiple processors sharing common data pool. Show less

With increasing complexity of SoCs and reduced execution cycle time, System Verilog assertions have become an integral part of verification environment. Assertions help in reducing the number of directed tests with an added advantage of reduction in effort and run-time in addition to providing verification coverage. Assertions can be deployed at various points in the design for verifying multiple aspects like resets, clocks and pads in the SoC. In this article, we will be highlighting the grey… Show more

With increasing complexity of SoCs and reduced execution cycle time, System Verilog assertions have become an integral part of verification environment. Assertions help in reducing the number of directed tests with an added advantage of reduction in effort and run-time in addition to providing verification coverage. Assertions can be deployed at various points in the design for verifying multiple aspects like resets, clocks and pads in the SoC. In this article, we will be highlighting the grey areas in which assertions come handy. We will also be discussing the methodology for efficiently generating assertions and then simply integrating them in the testbench environment using plug-n-play technique. Show less

As the complexities of SoCs are increasing day by day, multiple clock sources are available in SoCs, which provide clocks of wide frequency ranges (varying from KHz range to MHz range). Moreover depending upon the power and functionality requirements, we can have different power modes, say full power modes and low power modes and ultra-low power modes in SoC. Verification of all the clock sources is a tedious work, Further the complexity increases if we make a transition from one mode to… Show more

As the complexities of SoCs are increasing day by day, multiple clock sources are available in SoCs, which provide clocks of wide frequency ranges (varying from KHz range to MHz range). Moreover depending upon the power and functionality requirements, we can have different power modes, say full power modes and low power modes and ultra-low power modes in SoC. Verification of all the clock sources is a tedious work, Further the complexity increases if we make a transition from one mode to another mode, say sweeping past across all modes and having different clock configurations in each mode. So in this case, we shall have to cover (2m * 2n * p) cases, where n is the number of possible mode transitions and m is the available clock sources, p is the number of system clock sources. In this paper we shall present a matrix based approach to verify the entire clocking scheme of a SoC. The paper covers the methodological approach to find out the applicable scenarios and verification of such scenarios using directed test cases, system verilog assertions and glitch monitors to check any glitch in the clock, any abnormal behavior or any other design issue. Using this verification approach, multiple design bugs have been uncovered in SoCs.
Also covered by : http://www.testandverification.com/thought-leadership/matrix-based-clock-verification-uncovers-soc-bugs-5-june-2015/ Show less

Dynamic Frequency Scaling (DFS) is a feature in power critical SoCs where different clocks going to different modules can switch their frequencies on the fly, even in the middle of ongoing transactions, to reduce power consumption or heat generation. The main challenge is that if any transaction is ongoing and frequency scaling takes place, there should be no loss of data, the chip should not get stuck anywhere and all the modules should work seamlessly across the DFS. In this paper, an… Show more

Dynamic Frequency Scaling (DFS) is a feature in power critical SoCs where different clocks going to different modules can switch their frequencies on the fly, even in the middle of ongoing transactions, to reduce power consumption or heat generation. The main challenge is that if any transaction is ongoing and frequency scaling takes place, there should be no loss of data, the chip should not get stuck anywhere and all the modules should work seamlessly across the DFS. In this paper, an approach has been given to verify the integration and functionality of Dynamic Frequency Scaling in the SoC using multiple checks like assertions, frequency monitors and randomized test cases which we can use in the testbench environment. With this approach, multiple design bugs have been uncovered in the SoCs. Show less