feat(vcr-sel): VCR-SEL-001 increment 1 — verified selector rule DSL, wired flag-off (#242) - #623
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…wired flag-off (#242) The first wired increment of the Rocq-discharged selector DSL, per docs/design/vcr-sel-001-first-increment.md — a hand-written select_default arm is served from a verified rule without moving a byte of frozen output. - Rule table (crates/synth-synthesis/src/sel_dsl/mod.rs RULES): declarative op -> parameterized ARM sequence, registers as variables, side conditions explicit. Tier-A six (i32 add/sub/mul/and/or/xor) + tier-B i32.rotl with the SideCondition::NotAlias(Rs, Rn) scratch constraint carried in the rule format and enforced Ok-or-Err in the generated code. - Generator emits plain Rust lowerings COMMITTED to the tree (sel_dsl/generated.rs, rustfmt-stable, pinned by generated_lowering_is_up_to_date; SYNTH_SEL_DSL_REGEN=1 to regenerate). - select_default keeps dispatch: the seven migrated arms delegate to the generated rules behind SYNTH_SEL_DSL (default OFF) — OFF keeps the original hand-written bodies, byte-identical by construction. The exhaustive WasmOp match stays. - Rocq: coq/Synth/Synth/VcrSelRules.v — one universally-quantified T1 theorem per rule, 7 Qed / 0 Admitted, naming 1:1 (rule_X <-> rule_X_correct); tier-A via synth_binop_proof_poly verbatim, rotl via the pilot's stepped proof with the rs <> rn hypothesis. - Coverage gate: //coq:verify_proofs is now a test_suite = :rocq_proofs + :vcr_sel_rules_coverage (manifest pinned to RULES by a cargo test; a rule without its Qed cannot merge). Negative-tested both failure modes. - Gate 1 (mirror-pin, #511/#513 pattern): hand-written arm == generated rule ArmOp sequences for all 7 rules. Gate 2: frozen_codegen_bytes 9/9 green with flag OFF and with SYNTH_SEL_DSL=1. - artifacts: VCR-SEL-001 approved -> implemented (flip + re-freeze ritual still owed before verified). Refs #242. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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README: North-Star section rewritten — gale's 2026-06 flat_flight numbers (315 cyc / 3.18x, 61% redundant consts, 17 spills) become historical motivation; shipped v0.19-v0.30.2 arc documented (VCR-RA-001 verified default-on Belady spilling, const-CSE default-on gale-confirmed, lever ladder, #615 A32 i64 completeness + 221-variant tripwire, ordeal default verify engine); in-flight table (VCR-SEL-001 PR #623, VCR-PERF-002 PR #624, SYNTH_SPILL_ON_EXHAUST silicon-gated). Crate map gains riscv/aarch64 backends; synth-verify row and brittle test count fixed. Retains the previous session's uncommitted feature-table/proof-count refresh (verified: 298 Qed / 9 Admitted by recount). CLAUDE.md: backends line, proof status (298 Qed, i64 T1 parity, admit breakdown), North Star tracks updated to verified/in-review statuses, Track C noted as CI-gated, brittle test count removed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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README: North-Star section rewritten — gale's 2026-06 flat_flight numbers (315 cyc / 3.18x, 61% redundant consts, 17 spills) become historical motivation; shipped v0.19-v0.30.2 arc documented (VCR-RA-001 verified default-on Belady spilling, const-CSE default-on gale-confirmed, lever ladder, #615 A32 i64 completeness + 221-variant tripwire, ordeal default verify engine); in-flight table (VCR-SEL-001 PR #623, VCR-PERF-002 PR #624, SYNTH_SPILL_ON_EXHAUST silicon-gated). Crate map gains riscv/aarch64 backends; synth-verify row and brittle test count fixed. Retains the previous session's uncommitted feature-table/proof-count refresh (verified: 298 Qed / 9 Admitted by recount). CLAUDE.md: backends line, proof status (298 Qed, i64 T1 parity, admit breakdown), North Star tracks updated to verified/in-review statuses, Track C noted as CI-gated, brittle test count removed. Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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… in the verified selector DSL (#242) (#639) Extends the VCR-SEL-001 rule table (increment 1, PR #623) with 14 new Rocq-discharged rules, 21 total, each with its 1:1 Qed theorem in coq/Synth/Synth/VcrSelRules.v (21/21 Qed, 0 Admitted): - i32 register shifts shl/shr_s/shr_u + rotr: measured tier-A (single instruction, no scratch), discharged by synth_binop_proof_poly; delegated in BOTH selectors behind SYNTH_SEL_DSL (default OFF). - the ten i32 comparisons (CMP+SetCond shape, modeled as CMP; MOV rd #0; MOVcc rd #1 per the Compilation.v convention): no aliasing side conditions; 7/10 via synth_cmp_binop_proof_poly, ne/lt_s/lt_u register-generalized from their CorrectnessI32.v ancestors. Delegated in select_with_stack's reg-reg arm only — select_default's bare-Cmp arms are production-unreachable and unprovable as T1 (no result register), documented holdout; the #258 imm-fold peephole stays hand-written on both flag settings (pinned). Mirror-pins: generated_rules_match_handwritten_arms (11 rules), select_with_stack_rules_byte_identical (14 rules, non-vacuity window), cmp_imm_fold_path_stays_handwritten. OFF ≡ baseline by construction. Provenance: salvaged from an interrupted session (2026-07-08, session limit at 129 tool uses); this commit captures the on-disk work verbatim before verification gates. Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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First wired increment of the Rocq-discharged verified selector DSL per docs/design/vcr-sel-001-first-increment.md (#609 scope): rule table for the tier-A six (i32 add/sub/mul/and/or/xor) + tier-B i32.rotl (explicit rs≠rn side condition), generated Rust lowerings committed to the tree, select_default arms delegate behind SYNTH_SEL_DSL (default OFF — OFF ≡ baseline byte-identical), one T1 theorem per rule in coq/Synth/Synth/VcrSelRules.v with a coverage check that fails the //coq build if any rule lacks its Qed.
PROVENANCE / GATE NOTE: implemented and committed by an agent that hit the session limit before final verification could be reported. The commit message records the intended contract; CI is the gate — Bazel Build & Proofs must show the VcrSelRules Qeds + coverage check, frozen anchors must be untouched (flag off), full test/clippy/fmt must pass. Do not merge on anything less.
Refs #242.
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