Microvia reliability: understand interfaces and thermal exposure

Depth-to-diameter ratio affects the process challenge, but target-interface preparation, deposited copper, voids and the local material system also matter. Stacked structures add interfaces in a compact vertical route; staggered structures use lateral space and do not remove every process risk.

Use the calculator to make geometry explicit. It deliberately reports no universal pass/fail ratio. Compare the values with the fabricator’s released rules for the actual dielectric and process, then discuss the evidence supporting that construction.

Define the expected PCB assembly and rework exposures, conditioning and relevant service stresses. A test plan should say when resistance is measured and how failures are detected, rather than recording only a final visual inspection.

For PCB manufacturing acceptance, distinguish qualification of a construction from acceptance of a production lot. A historical test on a different material or via arrangement should not silently qualify a new structure. Ask what changed and whether the previous evidence remains representative.

When a problem occurs, retain board and lot identification, stack-up revision, exposure record and electrical data. Cross-section selection should follow the suspected interface and the test evidence.

Do not diagnose every intermittent connection as a microvia defect from a symptom alone. Review the assembly and interconnect path. The companion acceptance-planning page explains how to specify records and criteria before the next build.