PCB Etching Process: Acid, Alkaline and Advanced Methods

PCB etching is the chemical removal of unwanted copper from a copper-clad laminate, leaving behind only the traces and pads protected by a resist. In volume production it happens in a conveyorized spray chamber, using acidic cupric chloride on inner layers and alkaline ammoniacal etchant on outer layers. The etchant attacks sideways as well as downward, so the copper you get is always narrower than the artwork you drew — and controlling that gap is what separates a 4 mil process from a 3 mil one.

This guide covers how copper etching works, which chemistry your fabricator uses and why, the etch factor and undercut math that decides your finished trace width, what mSAP changes, and the design rules that keep your board inside IPC-6012 on the first build.

PCB etching in five lines:

• Etching is subtractive. Copper under dry film or plated tin survives; exposed copper dissolves.
• Inner layers run acidic cupric chloride, outer layers run alkaline ammoniacal etchant — because acid would strip the plated tin resist.
• Etch factor is copper thickness divided by undercut per side. At an etch factor of 3 on 1 oz copper, each edge loses about 12 µm, so a 150 µm trace finishes near 127 µm uncompensated.
• Copper weight sets your floor: roughly 100/100 µm line and space on 1 oz, 75/75 µm on half-ounce, 175/200 µm on 2 oz.
• Plasma and laser etching are real processes, but in volume PCB fab they handle desmear, etchback and flex — not copper patterning.

What Is PCB Etching and How Copper Etching Works

PCB etching is a subtractive process. You start with laminate already fully clad in copper foil — commonly 12 µm (⅓ oz), 17.5 µm (½ oz) or 35 µm (1 oz) — and remove everything that is not circuitry. Selectivity comes from the resist: an imaged dry film on inner layers, or electroplated tin on outer layers. Wherever the resist sits, copper survives.

Two chemistries do the work. Acidic cupric chloride (CuCl₂ in hydrochloric acid) oxidizes metallic copper into cuprous chloride, which is regenerated back to the active cupric form with hydrochloric acid and either hydrogen peroxide or chlorine. Alkaline etchant works through a copper-ammine complex, with ammonia and dissolved oxygen regenerating the active species in the sump. Both run as continuously regenerated baths rather than batches, because an etch line that stops to dump chemistry is an etch line that is not making boards.

Physically, etching happens in a horizontal spray chamber. Panels ride a conveyor at roughly 2.5–3.0 m/min through banks of nozzles spraying etchant at around 2 kg/cm² onto both faces, with the bath held near 50 °C ±1 °C. Etching sits in the middle of PCB manufacturing — after imaging and developing, before oxide treatment and lamination on inner layers, or before tin stripping and solder mask on outer layers.

Temperature is the strongest lever on etch rate. As a rule of thumb every 10 °C rise roughly doubles it, which is exactly why nobody just turns the heat up: a faster etch is also a more isotropic etch, so sideways attack grows along with downward attack.

Here is the part designers rarely hear. The top and bottom faces of the same panel do not etch identically. Spent etchant puddles on the upward-facing surface and shields the copper underneath, while the bottom face drains continuously and keeps seeing fresh chemistry. The leading edge of a panel enters the chamber dry and etches hardest of all. Fabs compensate with asymmetric top and bottom spray pressure, and newer etchers delay the first spray bars — but a small top-to-bottom width difference is a normal property of the process, not a defect report waiting to happen.

Acid vs Alkaline Etching: Which Etchant Your Fab Uses and Why

The choice between acidic and alkaline etching is not a quality contest. It is decided by what resist is sitting on the panel.

Inner layers carry dry film photoresist, which tolerates acid. Acidic cupric chloride is the workhorse there: steady etch rate, high copper-holding capacity, straightforward regeneration, and a spent bath pure enough to be sold rather than treated as waste. Ferric chloride — typically run near 36 °Bé with 1.5–2% free HCl — etches copper well but is costly to dispose of, so it survives mainly in prototyping and small shops.

Outer layers are pattern plated: copper first, then a thin tin layer that acts as the etch resist. Put that panel into cupric chloride and the acid attacks the tin before the copper etch finishes. Alkaline ammoniacal etchant leaves tin alone, etches fast, and holds a lot of dissolved copper. That, not speed, is the reason nearly every outer layer you have ever ordered was etched in ammonia.

Alkaline chemistry is also the more temperamental of the two. Etch rate depends on free ammonia, and free ammonia depends steeply on pH: near pH 8.25 only about a tenth of the ammonia present is in the free, active form, and by pH 7.25 it is closer to one percent. Bath density is held by a Baumé controller — good ones hold specific gravity to about ±0.001 — and temperature usually stays in the 43–49 °C band, because the extra rate available above that arrives with extra undercut. Let an alkaline bath sit idle for more than a couple of days and it can sludge out irreversibly.

Parameter	Acidic (cupric chloride)	Alkaline (ammoniacal)
Typical use	Inner layers, fine line inner cores, some microwave panels	Outer layers after pattern plating
Compatible resist	Dry film photoresist only — dissolves tin	Plated tin or tin-lead, and dry film
Relative etch rate	Slower, especially at low free acid	Faster
Undercut behaviour	Better control, typical etch factor 3.0–3.5	More lateral attack, typical etch factor 2.5–3.0
Copper capacity	Moderate, held below saturation to stay sludge-free	High — the reason it survives heavy outer-layer loads
Regeneration	HCl plus hydrogen peroxide or chlorine; spent etchant is saleable	Ammonia and ammonium chloride replenisher, oxygen-driven
Key control variables	Free HCl, specific gravity, temperature	pH near 8, specific gravity (±0.001), temperature 43–49 °C
Main headache	Slow rate, acid fume handling	Ammonia venting, sludge-out if the bath sits idle

The PCB Etching Process Step by Step

There are two distinct etch flows on a multilayer board, and they are not variations of one recipe.

Inner Layer Etching: Print and Etch

1. Clean and micro-etch the copper foil so the dry film bonds to a uniformly roughened surface.
2. Laminate dry film photoresist to both faces of the core.
3. Expose the image with laser direct imaging or a glass phototool, then develop away the unexposed film.
4. Etch in the acidic spray chamber. All copper not under film is removed in a single pass.
5. Strip the remaining dry film, leaving bare copper circuitry.
6. Run automated optical inspection on every core. Once cores are pressed with prepreg, an inner trace is physically unreachable, so AOI here is a yield gate, not an option.

Outer Layer Etching: Pattern Plate and Etch

1. Drill, desmear and deposit electroless copper so hole walls are conductive.
2. Image the outer layers with dry film, this time opening the areas that will become circuitry.
3. Electroplate copper into those openings to final thickness, then plate a thin tin layer on top as the etch resist.
4. Strip the dry film, exposing the base copper between the plated features.
5. Alkaline etch away that exposed base copper.
6. Strip the tin, then inspect with AOI and electrical test before solder mask.

One failure mode belongs entirely to the outer-layer flow. Plated tin tends to grow a slight overhang past the edge of the dry film, and photoresist trapped under that lip does not strip cleanly. Unstripped resist blocks the etchant, leaving a thin copper foot alongside the trace. The foot narrows finished spacing, and on tight-pitch designs it is enough to fail spacing at the last inspection gate — after essentially all the cost is already in the panel.

Before any of this, CAM applies etch compensation to your data. When your Gerber files are converted into production tooling, every conductor is widened by the amount the fab expects to lose sideways. That is standard practice at any professional facility, and it is why you should release finished dimensions and let the fabricator apply their own compensation, rather than pre-widening traces yourself and getting compensated twice.

Etch Factor and Undercut: Why Your Trace Finishes Narrower Than You Drew

Undercut is the copper removed laterally beneath the resist edge, measured per side. Etch factor is the ratio of copper thickness to that lateral loss:

Etch factor = copper thickness ÷ undercut per side

An etch factor of 3 on 35 µm copper means roughly 11.7 µm of copper is lost from each edge — call it 12 µm — so a 150 µm drawn trace finishes near 127 µm if nobody compensates. The cross-section is not a rectangle either. It is a trapezoid, wide at the top where the resist protected it and narrow at the base where the etchant worked longest.

Conventions differ between suppliers. Some quote etch factor against total width loss rather than loss per side, which makes their number look twice as good. Confirm which definition a fab is using before you conclude one process is better than another.

Production etch factors on a conveyorized copper line typically land between 2.5 and 3.5. Figures above 5 appear in the literature, but they come from plasma and semiconductor processes, not from a spray etcher moving panels at 3 m/min.

Starting copper	Thickness	Undercut per side at EF 3	Total width loss	Practical min line/space (subtractive)
⅓ oz	12 µm	~4 µm	~8 µm	50/50 µm (2/2 mil)
½ oz	17.5 µm	~6 µm	~12 µm	75/75 µm (3/3 mil)
1 oz	35 µm	~12 µm	~23 µm	100/100 µm (4/4 mil)
2 oz	70 µm	~23 µm	~47 µm	175/200 µm (7/8 mil)
3 oz	105 µm	~35 µm	~70 µm	250/300 µm (10/12 mil)

Those figures are based on starting foil. Outer layers gain copper through plating, so a board ordered as 1 oz outer can finish near 45–60 µm, and the compensation applied is calculated from that plated thickness. It is one of the reasons outer-layer minimum line and space is usually coarser than inner-layer capability on the same fab’s data sheet.

Undercut is a signal integrity problem, not a cosmetic one. Trace width is a first-order term in every impedance equation. Losing about 0.5 mil of width per side on a 1 oz stripline moves a 100 Ω differential pair by roughly 2.5 Ω, before Dk tolerance and copper thickness variation are added. At ±10% impedance you have room to absorb that. At ±5% you do not, and you need the fabricator’s compensated stack-up simulation instead of a textbook calculator.

The second thing designers underestimate is that etch factor is not one number for a whole panel. A trace isolated in an open field is surrounded by copper that must all be dissolved, and fresh etchant keeps arriving at it, so it etches longer and finishes narrower than the identical trace inside a dense fan-out where the etchant loads up locally. Large copper-free areas next to fine features are therefore a yield hazard, which is why fabs add thieving copper to open regions. On fine line designs, balancing copper distribution buys you more real width accuracy than arguing about chemistry ever will.

Advanced Etching Methods: Plasma, Laser, Flash Etch and mSAP

Search results are full of pages listing dry etching and laser etching as alternative ways to pattern PCB copper. In volume fabrication, they are not. Here is the truth: plasma and laser processes run constantly in a modern shop — just not to define your traces.

Plasma generates reactive species that attack polymers, not copper. Its real jobs are desmear and etchback inside drilled holes, and it is the preferred route on polyimide flex and rigid-flex, where wet permanganate struggles. Positive etchback removes dielectric so copper is exposed on three sides inside the barrel and can be plated all round; negative etchback recesses the copper instead. Where etchback is specified, IPC-6013 calls for roughly 0.001–0.003 in (25–76 µm) of exposed copper, and negative etchback on Class 3 is held near 0.0005 in (13 µm).

Laser structuring removes copper with no chemistry and no mechanical stress, which is useful for one-off prototypes, repairs and laser direct structuring on molded parts. Its limitation is area throughput: ablating every unwanted square millimetre of copper on a production panel takes orders of magnitude longer than spraying it for a minute.

The etch step actually moving the fine-line frontier is the smallest one. In mSAP the panel starts with only 2–5 µm of copper foil, the pattern is electroplated up between resist walls, and a short flash etch clears the thin seed layer at the end. Because there is so little copper to remove laterally, undercut nearly disappears and sidewalls come out close to vertical. SAP goes further still, starting from sub-micron electroless copper.

Process	Starting copper	Typical line/space	Sidewall	Where it is used
Subtractive print and etch	12–70 µm foil	75–125 µm	Trapezoid	Almost all rigid PCB and standard HDI
mSAP	2–5 µm foil plus plating	20–40 µm	Near vertical	Phone substrate-like PCBs, high-end HDI
SAP	Sub-micron electroless	10–20 µm	Vertical	IC substrates, advanced packaging

The trade-off is blunt. Subtractive etching is mature, inexpensive and available at every fabricator on earth, and it runs out of headroom somewhere around 50–75 µm line and space. mSAP buys you 20–40 µm, but costs several times more per panel, needs different laminate and imaging equipment, and has a far smaller supplier base. Most designs that believe they need mSAP actually need half-ounce copper and a copper-balanced layout.

Common PCB Etching Defects and What Causes Them

• Over-etch: necked-down conductors, nicks and opens. Causes are excess dwell time, a bath running hot, or spray pressure set too high. IPC-6012 allows a local conductor width reduction of 20% for Class 2 and Class 3 (30% for Class 1), and defaults minimum conductor width to 80% of the value in your procurement data when you never specified one. Most arguments that start with “the traces look thin” end right there.
• Under-etch: copper residue between conductors, shorts, and copper feet. Causes are conveyor speed too high, an exhausted or cold bath, clogged nozzles, or unstripped resist under a tin lip.
• Excessive undercut: weak trapezoidal traces, impedance drifting high, reduced peel strength. Causes are long dwell, an aggressive hot bath, or thin and poorly adhered dry film.
• Uneven etch: top-to-bottom or leading-edge-to-trailing-edge variation from puddling and spray imbalance. This is why coupons belong on the panel rails and not only inside the array.
• Resist breakdown: pinholes, film lifting and ragged conductor edges. Causes are contaminated copper before film lamination, wrong exposure energy, or a resist and etchant pairing that were never compatible.
• Copper slivers: acute-angle intersections and isolated copper islands that break loose during etching and land somewhere else on the panel, creating shorts. Clean these up in layout, because no etcher can remove them safely.

A representative case. An industrial motor-drive customer moved outer-layer copper from 1 oz to 2 oz to pull down the temperature rise on a FET stage, and kept the existing 4 mil / 4 mil routing under a 0.5 mm pitch BGA. The heavier copper needed roughly twice the etch dwell, the fan-out traces lost about 23 µm per side instead of 12 µm, and AOI began flagging necked conductors and residual copper on the same panels. The fix was not a better etcher. Signal layers moved to half-ounce inner cores, 2 oz stayed on dedicated power layers, and the fan-out went back inside the fab’s 1 oz rule set. Rework fell from roughly a third of panels to under 2%.

Acceptance is judged visually against IPC-A-600 and dimensionally against IPC-6012. Reputable fabs run AOI on each inner core before lamination and again after outer-layer etch, for the simple reason that a buried trace cannot be repaired once the stack is pressed.

PCB Etching DFM Checklist Before You Release Your Files

1. Specify finished conductor width, not artwork width, and say so on the fabrication drawing. State the IPC-6012 class in the same note.
2. Ask your fabricator for their etch compensation values by copper weight and layer type. Any serious shop keeps an empirical table calibrated to its own equipment. Take theirs over any formula in this article.
3. Match line and space to copper weight. If a rail needs 2 oz, put the 2 oz on a dedicated layer and keep 4 mil routing on half-ounce or 1 oz layers.
4. Balance copper across each layer and allow thieving in open areas. If thieving is forbidden inside an RF or antenna zone, mark that zone explicitly rather than leaving the fab to guess.
5. Give impedance as a target plus tolerance with the layers identified, and let the fab set final widths. Locking trace width and impedance at the same time creates two constraints that fight each other.
6. Delete acute angles, stub fragments and isolated copper slivers before release.
7. Send the complete data set — Gerber or ODB++, drill, netlist and stack-up — for a DFM review before you place the order, not after the first article fails.
8. On impedance-critical or Class 3 builds, ask for microsection coupons and TDR data with the shipment. A real cross-section tells you the etch factor your boards were actually built at, which is the only number that matters next time.

Frequently Asked Questions About PCB Etching

What chemical is used to etch a PCB?

Production fabs use acidic cupric chloride on inner layers and alkaline ammoniacal etchant on outer layers. Ferric chloride and ammonium persulfate still appear in prototyping and hobby work. All of them dissolve exposed copper while leaving dry film photoresist or plated tin resist intact.

What is undercut in PCB etching?

Undercut is the copper etched sideways beneath the resist edge, measured per side. It leaves a trapezoidal trace, narrower at the base than at the top. Undercut reduces conductor cross-section, pushes impedance higher and weakens adhesion, which is why fabricators pre-widen artwork to compensate for it.

How do you calculate etch factor?

Etch factor equals copper thickness divided by undercut per side. Etching 35 µm copper with about 12 µm of lateral loss per edge gives an etch factor near 3. Higher numbers mean straighter sidewalls. Always confirm which convention a supplier quotes, since some use total width loss.

Why do inner and outer layers use different etchants?

Resist compatibility decides it. Inner layers are protected by dry film, which survives acid, so fabs use cupric chloride for its finer control. Outer layers are protected by electroplated tin, which acid would dissolve, so they run alkaline ammoniacal etchant that attacks copper but leaves tin alone.

Does etching affect PCB impedance?

Yes. Trace width is a primary variable in impedance, so undercut shifts the finished value. Losing roughly 0.5 mil per side on a 1 oz stripline can move a 100 Ω differential pair by about 2.5 Ω. Specify impedance with a tolerance and let the fab set widths.

What is the minimum trace width subtractive etching can hold?

Mainstream subtractive etching holds about 100 µm (4 mil) line and space on 1 oz copper and 75 µm (3 mil) on half-ounce. Below roughly 50 µm, yields fall away and mSAP takes over, reaching 20–40 µm with near-vertical sidewalls.

Is etchback the same as PCB etching?

No. Etching defines the conductors on a layer. Etchback is a hole-wall process performed after drilling and desmear, removing dielectric so inner-layer copper is exposed inside the barrel for better plating. IPC-6013 defines the permitted amounts when a drawing calls for it.

Getting the PCB Etching Process Right on Your Next Build

PCB etching is where a drawing stops being a drawing. Copper weight, line and space, impedance targets and copper balance are all requests until the panel enters the spray chamber. What comes out is a trapezoid with a per-side loss you either planned for or did not, produced by a chemistry chosen according to which resist was on the panel. Designers who release finished dimensions, match geometry to copper weight and ask for their fab’s compensation table almost never end up arguing about trace width after the fact.

For PCB manufacturing, release the required finished conductor dimensions, spacing and copper construction alongside the stack-up. Agree how the fabricator will compensate the artwork and verify the finished geometry, particularly where etch variation affects current capacity or controlled impedance.